CMSIS-Core (Cortex-A): Translation Table Base Registers (TTBR0/TTBR1)

| CMSIS-Core (Cortex-A) Version 1.2.1 CMSIS-Core support for Cortex-A processor-based devices

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Translation Table Base Registers (TTBR0/TTBR1)
Core Register Access

TTBRn holds the base address of translation table n, and information about the memory it occupies. More...

## Functions

__STATIC_FORCEINLINE uint32_t | __get_TTBR0 (void)
| Get TTBR0. More...
__STATIC_FORCEINLINE void | __set_TTBR0 (uint32_t ttbr0)
| Set TTBR0. More...

## Description

32-bit TTBR format

Bits | Name | Function
--- | --- | ---
[31:x] | BADDR | Translation table base address, bits[31:x].
[x-1:7] | - | Reserved.
[6] | IRGN[0] | Inner region bit 0.
[5] | NOS | Not Outer Shareable bit.
[4:3] | RGN | Region bits.
[2] | - | Reserved.
[1] | S | Shareable bit.
[0] | C/IRGN[1] | Cacheable bit. / Inner region bit 1.

Note
  The width of TTBR0 BADDR field depends on the setting in TTBCR N field, giving `x=14-N`.
  The width of TTBR1 BADDR field is fixed at `x=14`.

64-bit TTBR format

Bits | Name | Function
--- | --- | ---
[63:56] | - | Reserved.
[55:48] | ASID | An ASID for the translation table base address.
[47:40] | - | Reserved.
[39:x] | BADDR | Translation table base address, bits[39:x].
[x-1:0] | - | Reserved.

Note
  The width of TBBR0/TBBR1 BADDR fields depends on the settings in TTBCR T0SZ/T1SZ fields respectively, giving `x=14-TnSZ`.

Consider using __get_TTBR0 and __set_TTBR0 for accessing TTBR0 register.

## Function Documentation

__STATIC_INLINE uint32_t __get_TTBR0 | ( | void |  | ) |

This function returns the value of the Translation Table Base Register 0.

Returns
  Translation Table Base Register 0 value

This function returns the value of the Translation Table Base Register 0.

__STATIC_INLINE void __set_TTBR0 | ( | uint32_t | ttbr0 | ) |

This function assigns the given value to the Translation Table Base Register 0.

Parameters

  [in] | ttbr0 | Translation Table Base Register 0 value to set

This function assigns the given value to the Translation Table Base Register 0.