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Initial snapshot: Aliro applet, harness, Nucleo NFC10A1 reader port

Browse Source 
Three components, all bench-validated to varying depths:

- applet/: CSA Aliro v1.0 Java Card applet for J3R180. AUTH0 + AUTH1
  expedited-standard flow end-to-end green via PC/SC bench reader
  (aliro-bench-test). Userland AES-256-GCM and HMAC-SHA-256 layered
  on top of J3R180's primitives because the card lacks both natively.
  P-256 curve params seeded explicitly per J3R180's quirk.

- harness/: Python orchestrator (aliro-trustgen, aliro-personalize,
  aliro-bench-test) for trust-bundle generation, card personalization
  via PersonalizationApplet, and PC/SC AUTH0+AUTH1 transactions. 126
  pytest cases passing.

- reader/STM32CubeExpansion_ALIRO_V1_0_0/: ST X-CUBE-ALIRO V1.0.0
  with our NFC10A1 port (NUCLEO-U545RE-Q + X-NUCLEO-NFC10A1, ST25R200
  shared with NFC09A1). nfc10-only/ project, NFC10A1 BSP shim,
  ALIRO_TRUST_OVERRIDE include into vendor's provisioning.c, and an
  ALIRO_APDU_TRACE wrapper around demoTransceiveBlocking. Boots,
  detects the J3R180, completes SELECT + AUTH0; AUTH1 currently fails
  with RFAL ERR_PROTO (0xB) — under investigation, see
  docs/plans/2026-04-20-nucleo-nfc10a1-port.md and bench-notes/.

Excluded: x-cube-aliro.zip vendor archive, harness/.venv, build dirs,
generated aliro_trust.h (contains private reader scalar), all PEMs.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
Dangerous Things
2026-05-02 10:17:46 -07:00
commit 782074f6ae
8786 changed files with 2902373 additions and 0 deletions
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414
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/*
* Copyright (c) 2016, 2019 ARM Limited.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __ARM_COMPUTE_NEMATH_H__
#define __ARM_COMPUTE_NEMATH_H__
#if defined(ARM_MATH_NEON)
/** Calculate floor of a vector.
*
* @param[in] val Input vector value in F32 format.
*
* @return The calculated floor vector.
*/
static inline float32x4_t vfloorq_f32(float32x4_t val);
/** Calculate inverse square root.
*
* @param[in] x Input value.
*
* @return The calculated inverse square root.
*/
static inline float32x2_t vinvsqrt_f32(float32x2_t x);
/** Calculate inverse square root.
*
* @param[in] x Input value.
*
* @return The calculated inverse square root.
*/
static inline float32x4_t vinvsqrtq_f32(float32x4_t x);
/** Calculate reciprocal.
*
* @param[in] x Input value.
*
* @return The calculated reciprocal.
*/
static inline float32x2_t vinv_f32(float32x2_t x);
/** Calculate reciprocal.
*
* @param[in] x Input value.
*
* @return The calculated reciprocal.
*/
static inline float32x4_t vinvq_f32(float32x4_t x);
/** Perform a 7th degree polynomial approximation using Estrin's method.
*
* @param[in] x Input vector value in F32 format.
* @param[in] coeffs Polynomial coefficients table. (array of flattened float32x4_t vectors)
*
* @return The calculated approximation.
*/
static inline float32x4_t vtaylor_polyq_f32(float32x4_t x, const float32_t *coeffs);
/** Calculate exponential
*
* @param[in] x Input vector value in F32 format.
*
* @return The calculated exponent.
*/
static inline float32x4_t vexpq_f32(float32x4_t x);
/** Calculate logarithm
*
* @param[in] x Input vector value in F32 format.
*
* @return The calculated logarithm.
*/
static inline float32x4_t vlogq_f32(float32x4_t x);
/** Calculate hyperbolic tangent.
*
* tanh(x) = (e^2x - 1)/(e^2x + 1)
*
* @note We clamp x to [-5,5] to avoid overflowing issues.
*
* @param[in] val Input vector value in F32 format.
*
* @return The calculated Hyperbolic Tangent.
*/
static inline float32x4_t vtanhq_f32(float32x4_t val);
/** Calculate n power of a number.
*
* pow(x,n) = e^(n*log(x))
*
* @param[in] val Input vector value in F32 format.
* @param[in] n Powers to raise the input to.
*
* @return The calculated power.
*/
static inline float32x4_t vpowq_f32(float32x4_t val, float32x4_t n);
#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
/** Calculate hyperbolic tangent.
*
* tanh(x) = (e^2x - 1)/(e^2x + 1)
*
* @note We clamp x to [-5,5] to avoid overflowing issues.
*
* @param[in] val Input vector value in F32 format.
*
* @return The calculated Hyperbolic Tangent.
*/
static inline float16x8_t vtanhq_f16(float16x8_t val);
/** Calculate reciprocal.
*
* @param[in] x Input value.
*
* @return The calculated reciprocal.
*/
static inline float16x4_t vinv_f16(float16x4_t x);
/** Calculate reciprocal.
*
* @param[in] x Input value.
*
* @return The calculated reciprocal.
*/
static inline float16x8_t vinvq_f16(float16x8_t x);
/** Calculate inverse square root.
*
* @param[in] x Input value.
*
* @return The calculated inverse square root.
*/
static inline float16x4_t vinvsqrt_f16(float16x4_t x);
/** Calculate inverse square root.
*
* @param[in] x Input value.
*
* @return The calculated inverse square root.
*/
static inline float16x8_t vinvsqrtq_f16(float16x8_t x);
/** Calculate exponential
*
* @param[in] x Input vector value in F16 format.
*
* @return The calculated exponent.
*/
static inline float16x8_t vexpq_f16(float16x8_t x);
/** Calculate n power of a number.
*
* pow(x,n) = e^(n*log(x))
*
* @param[in] val Input vector value in F16 format.
* @param[in] n Powers to raise the input to.
*
* @return The calculated power.
*/
static inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n);
#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
/** Exponent polynomial coefficients */
extern const float32_t exp_tab[4*8];
/** Logarithm polynomial coefficients */
extern const float32_t log_tab[4*8];
#ifndef DOXYGEN_SKIP_THIS
inline float32x4_t vfloorq_f32(float32x4_t val)
{
static const float32_t CONST_1[4] = {1.f,1.f,1.f,1.f};
const int32x4_t z = vcvtq_s32_f32(val);
const float32x4_t r = vcvtq_f32_s32(z);
return vbslq_f32(vcgtq_f32(r, val), vsubq_f32(r, vld1q_f32(CONST_1)), r);
}
inline float32x2_t vinvsqrt_f32(float32x2_t x)
{
float32x2_t sqrt_reciprocal = vrsqrte_f32(x);
sqrt_reciprocal = vmul_f32(vrsqrts_f32(vmul_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
sqrt_reciprocal = vmul_f32(vrsqrts_f32(vmul_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
return sqrt_reciprocal;
}
inline float32x4_t vinvsqrtq_f32(float32x4_t x)
{
float32x4_t sqrt_reciprocal = vrsqrteq_f32(x);
sqrt_reciprocal = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
sqrt_reciprocal = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
return sqrt_reciprocal;
}
inline float32x2_t vinv_f32(float32x2_t x)
{
float32x2_t recip = vrecpe_f32(x);
recip = vmul_f32(vrecps_f32(x, recip), recip);
recip = vmul_f32(vrecps_f32(x, recip), recip);
return recip;
}
inline float32x4_t vinvq_f32(float32x4_t x)
{
float32x4_t recip = vrecpeq_f32(x);
recip = vmulq_f32(vrecpsq_f32(x, recip), recip);
recip = vmulq_f32(vrecpsq_f32(x, recip), recip);
return recip;
}
inline float32x4_t vtaylor_polyq_f32(float32x4_t x, const float32_t *coeffs)
{
float32x4_t A = vmlaq_f32(vld1q_f32(&coeffs[4*0]), vld1q_f32(&coeffs[4*4]), x);
float32x4_t B = vmlaq_f32(vld1q_f32(&coeffs[4*2]), vld1q_f32(&coeffs[4*6]), x);
float32x4_t C = vmlaq_f32(vld1q_f32(&coeffs[4*1]), vld1q_f32(&coeffs[4*5]), x);
float32x4_t D = vmlaq_f32(vld1q_f32(&coeffs[4*3]), vld1q_f32(&coeffs[4*7]), x);
float32x4_t x2 = vmulq_f32(x, x);
float32x4_t x4 = vmulq_f32(x2, x2);
float32x4_t res = vmlaq_f32(vmlaq_f32(A, B, x2), vmlaq_f32(C, D, x2), x4);
return res;
}
inline float32x4_t vexpq_f32(float32x4_t x)
{
static const float32_t CONST_LN2[4] = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f}; // ln(2)
static const float32_t CONST_INV_LN2[4] = {1.4426950408f,1.4426950408f,1.4426950408f,1.4426950408f}; // 1/ln(2)
static const float32_t CONST_0[4] = {0.f,0.f,0.f,0.f};
static const int32_t CONST_NEGATIVE_126[4] = {-126,-126,-126,-126};
// Perform range reduction [-log(2),log(2)]
int32x4_t m = vcvtq_s32_f32(vmulq_f32(x, vld1q_f32(CONST_INV_LN2)));
float32x4_t val = vmlsq_f32(x, vcvtq_f32_s32(m), vld1q_f32(CONST_LN2));
// Polynomial Approximation
float32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
// Reconstruct
poly = vreinterpretq_f32_s32(vqaddq_s32(vreinterpretq_s32_f32(poly), vqshlq_n_s32(m, 23)));
poly = vbslq_f32(vcltq_s32(m, vld1q_s32(CONST_NEGATIVE_126)), vld1q_f32(CONST_0), poly);
return poly;
}
inline float32x4_t vlogq_f32(float32x4_t x)
{
static const int32_t CONST_127[4] = {127,127,127,127}; // 127
static const float32_t CONST_LN2[4] = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f}; // ln(2)
// Extract exponent
int32x4_t m = vsubq_s32(vreinterpretq_s32_u32(vshrq_n_u32(vreinterpretq_u32_f32(x), 23)), vld1q_s32(CONST_127));
float32x4_t val = vreinterpretq_f32_s32(vsubq_s32(vreinterpretq_s32_f32(x), vshlq_n_s32(m, 23)));
// Polynomial Approximation
float32x4_t poly = vtaylor_polyq_f32(val, log_tab);
// Reconstruct
poly = vmlaq_f32(poly, vcvtq_f32_s32(m), vld1q_f32(CONST_LN2));
return poly;
}
inline float32x4_t vtanhq_f32(float32x4_t val)
{
static const float32_t CONST_1[4] = {1.f,1.f,1.f,1.f};
static const float32_t CONST_2[4] = {2.f,2.f,2.f,2.f};
static const float32_t CONST_MIN_TANH[4] = {-10.f,-10.f,-10.f,-10.f};
static const float32_t CONST_MAX_TANH[4] = {10.f,10.f,10.f,10.f};
float32x4_t x = vminq_f32(vmaxq_f32(val, vld1q_f32(CONST_MIN_TANH)), vld1q_f32(CONST_MAX_TANH));
float32x4_t exp2x = vexpq_f32(vmulq_f32(vld1q_f32(CONST_2), x));
float32x4_t num = vsubq_f32(exp2x, vld1q_f32(CONST_1));
float32x4_t den = vaddq_f32(exp2x, vld1q_f32(CONST_1));
float32x4_t tanh = vmulq_f32(num, vinvq_f32(den));
return tanh;
}
inline float32x4_t vpowq_f32(float32x4_t val, float32x4_t n)
{
return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
}
#endif /* DOXYGEN_SKIP_THIS */
#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
/** Exponent polynomial coefficients */
/** Logarithm polynomial coefficients */
#ifndef DOXYGEN_SKIP_THIS
inline float16x8_t vfloorq_f16(float16x8_t val)
{
static const float16_t CONST_1[8] = {1.f,1.f,1.f,1.f,1.f,1.f,1.f,1.f};
const int16x8_t z = vcvtq_s16_f16(val);
const float16x8_t r = vcvtq_f16_s16(z);
return vbslq_f16(vcgtq_f16(r, val), vsubq_f16(r, vld1q_f16(CONST_1)), r);
}
inline float16x4_t vinvsqrt_f16(float16x4_t x)
{
float16x4_t sqrt_reciprocal = vrsqrte_f16(x);
sqrt_reciprocal = vmul_f16(vrsqrts_f16(vmul_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
sqrt_reciprocal = vmul_f16(vrsqrts_f16(vmul_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
return sqrt_reciprocal;
}
inline float16x8_t vinvsqrtq_f16(float16x8_t x)
{
float16x8_t sqrt_reciprocal = vrsqrteq_f16(x);
sqrt_reciprocal = vmulq_f16(vrsqrtsq_f16(vmulq_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
sqrt_reciprocal = vmulq_f16(vrsqrtsq_f16(vmulq_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
return sqrt_reciprocal;
}
inline float16x4_t vinv_f16(float16x4_t x)
{
float16x4_t recip = vrecpe_f16(x);
recip = vmul_f16(vrecps_f16(x, recip), recip);
recip = vmul_f16(vrecps_f16(x, recip), recip);
return recip;
}
inline float16x8_t vinvq_f16(float16x8_t x)
{
float16x8_t recip = vrecpeq_f16(x);
recip = vmulq_f16(vrecpsq_f16(x, recip), recip);
recip = vmulq_f16(vrecpsq_f16(x, recip), recip);
return recip;
}
inline float16x8_t vtanhq_f16(float16x8_t val)
{
const float16_t CONST_1[8] = {1.f,1.f,1.f,1.f,1.f,1.f,1.f,1.f};
const float16_t CONST_2[8] = {2.f,2.f,2.f,2.f,2.f,2.f,2.f,2.f};
const float16_t CONST_MIN_TANH[8] = {-10.f,-10.f,-10.f,-10.f,-10.f,-10.f,-10.f,-10.f};
const float16_t CONST_MAX_TANH[8] = {10.f,10.f,10.f,10.f,10.f,10.f,10.f,10.f};
const float16x8_t x = vminq_f16(vmaxq_f16(val, vld1q_f16(CONST_MIN_TANH)), vld1q_f16(CONST_MAX_TANH));
const float16x8_t exp2x = vexpq_f16(vmulq_f16(vld1q_f16(CONST_2), x));
const float16x8_t num = vsubq_f16(exp2x, vld1q_f16(CONST_1));
const float16x8_t den = vaddq_f16(exp2x, vld1q_f16(CONST_1));
const float16x8_t tanh = vmulq_f16(num, vinvq_f16(den));
return tanh;
}
inline float16x8_t vtaylor_polyq_f16(float16x8_t x, const float16_t *coeffs)
{
const float16x8_t A = vaddq_f16(vld1q_f16(&coeffs[8*0]), vmulq_f16(vld1q_f16(&coeffs[8*4]), x));
const float16x8_t B = vaddq_f16(vld1q_f16(&coeffs[8*2]), vmulq_f16(vld1q_f16(&coeffs[8*6]), x));
const float16x8_t C = vaddq_f16(vld1q_f16(&coeffs[8*1]), vmulq_f16(vld1q_f16(&coeffs[8*5]), x));
const float16x8_t D = vaddq_f16(vld1q_f16(&coeffs[8*3]), vmulq_f16(vld1q_f16(&coeffs[8*7]), x));
const float16x8_t x2 = vmulq_f16(x, x);
const float16x8_t x4 = vmulq_f16(x2, x2);
const float16x8_t res = vaddq_f16(vaddq_f16(A, vmulq_f16(B, x2)), vmulq_f16(vaddq_f16(C, vmulq_f16(D, x2)), x4));
return res;
}
inline float16x8_t vexpq_f16(float16x8_t x)
{
// TODO (COMPMID-1535) : Revisit FP16 approximations
const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x));
const float32x4_t x_low = vcvt_f32_f16(vget_low_f16(x));
const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vexpq_f32(x_low)), vexpq_f32(x_high));
return res;
}
inline float16x8_t vlogq_f16(float16x8_t x)
{
// TODO (COMPMID-1535) : Revisit FP16 approximations
const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x));
const float32x4_t x_low = vcvt_f32_f16(vget_low_f16(x));
const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vlogq_f32(x_low)), vlogq_f32(x_high));
return res;
}
inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n)
{
// TODO (giaiod01) - COMPMID-1535
float32x4_t n0_f32 = vcvt_f32_f16(vget_low_f16(n));
float32x4_t n1_f32 = vcvt_f32_f16(vget_high_f16(n));
float32x4_t val0_f32 = vcvt_f32_f16(vget_low_f16(val));
float32x4_t val1_f32 = vcvt_f32_f16(vget_high_f16(val));
float32x4_t res0_f32 = vexpq_f32(vmulq_f32(n0_f32, vlogq_f32(val0_f32)));
float32x4_t res1_f32 = vexpq_f32(vmulq_f32(n1_f32, vlogq_f32(val1_f32)));
return vcombine_f16(vcvt_f16_f32(res0_f32), vcvt_f16_f32(res1_f32));
}
#endif /* DOXYGEN_SKIP_THIS */
#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
#endif
#endif /* __ARM_COMPUTE_NEMATH_H__ */

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MIT License
Copyright (c) 2017-2019 ARM Software
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

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README
======
This folder is containing two files imported, and slightly modified, from the ComputeLibrary:
NEMath.h and arm_cl_tables.c
In the original compute library, there are instead two other files:
NEMath.h and NEMath.inl
NEMath.inl is included from NEMath.h whereas in this CMSIS DSP implementation, there is no NEMath.inl and its content is copied into NEMath.h
The tables contained in NEMath.inl have been moved to arm_cl_tables.c and finally the files are in C for the CMSIS DSP library and in C++ in the original Compute Library.
Otherwise, the features and implementations are the same : a few optimized Neon functions.
The license covering those files is different : It is a MIT license.
Other parts of the CMSIS-DSP are covered with an Apache-2.0 license.

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/*
* Copyright (c) 2016, 2019 ARM Limited.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "arm_math.h"
#include "NEMath.h"
#if defined(ARM_MATH_NEON)
/** Exponent polynomial coefficients */
const float32_t exp_tab[4*8] =
{
1.f,1.f,1.f,1.f,
0.0416598916054f,0.0416598916054f,0.0416598916054f,0.0416598916054f,
0.500000596046f,0.500000596046f,0.500000596046f,0.500000596046f,
0.0014122662833f,0.0014122662833f,0.0014122662833f,0.0014122662833f,
1.00000011921f,1.00000011921f,1.00000011921f,1.00000011921f,
0.00833693705499f,0.00833693705499f,0.00833693705499f,0.00833693705499f,
0.166665703058f,0.166665703058f,0.166665703058f,0.166665703058f,
0.000195780929062f,0.000195780929062f,0.000195780929062f,0.000195780929062f
};
/** Logarithm polynomial coefficients */
const float32_t log_tab[4*8] =
{
-2.29561495781f,-2.29561495781f,-2.29561495781f,-2.29561495781f,
-2.47071170807f,-2.47071170807f,-2.47071170807f,-2.47071170807f,
-5.68692588806f,-5.68692588806f,-5.68692588806f,-5.68692588806f,
-0.165253549814f,-0.165253549814f,-0.165253549814f,-0.165253549814f,
5.17591238022f,5.17591238022f,5.17591238022f,5.17591238022f,
0.844007015228f,0.844007015228f,0.844007015228f,0.844007015228f,
4.58445882797f,4.58445882797f,4.58445882797f,4.58445882797f,
0.0141278216615f,0.0141278216615f,0.0141278216615f,0.0141278216615f
};
#endif

4
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build/
*_debug/
EventRecorderStub.scvd
_ARMCM0/

8
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
#------------------------------------------------------------------------------

8
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
#------------------------------------------------------------------------------

9
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
#------------------------------------------------------------------------------

25
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM55_FP_MVE_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU)
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
#
cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU)
cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
#------------------------------------------------------------------------------

9
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
#------------------------------------------------------------------------------

10
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CMSIS DSP_Lib example arm_class_marks_example
The example is available for different targets:
Cortex-M0
Cortex-M3
Cortex-M4 with FPU
Cortex-M7 with single precision FPU
Cortex-M55 with double precision FPU, Integer + Floating Point MVE
The example is configured for Models Debugger

45
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cmake_minimum_required (VERSION 3.14)
project (arm_bayes_example VERSION 0.1)
# Needed to include the configBoot module
# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake)
set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..)
set(DSP ${ROOT}/CMSIS/DSP)
# Add DSP folder to module path
list(APPEND CMAKE_MODULE_PATH ${DSP})
###################################
#
# LIBRARIES
#
###################################
###########
#
# CMSIS DSP
#
add_subdirectory(../../../Source bin_dsp)
###################################
#
# TEST APPLICATION
#
###################################
add_executable(arm_bayes_example)
include(config)
configApp(arm_bayes_example ${ROOT})
target_sources(arm_bayes_example PRIVATE arm_bayes_example_f32.c)
### Sources and libs
target_link_libraries(arm_bayes_example PRIVATE CMSISDSP)

76
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

131
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/******************************************************************************
* @file startup_ARMCM0.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM0.h"
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10..31 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

56
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/**************************************************************************//**
* @file system_ARMCM0.c
* @brief CMSIS Device System Source File for
* ARMCM0 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM0.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}

76
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

135
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/******************************************************************************
* @file startup_ARMCM3.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM3.h"
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void) ;
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
__NO_RETURN void Default_Handler(void);
__NO_RETURN void Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
__NO_RETURN void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

65
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/**************************************************************************//**
* @file system_ARMCM3.c
* @brief CMSIS Device System Source File for
* ARMCM3 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM3.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

76
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

141
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c Normal file
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/******************************************************************************
* @file startup_ARMCM4.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
#include "ARMCM4.h"
#elif defined (ARMCM4_FP)
#include "ARMCM4_FP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
__NO_RETURN void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

81
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c Normal file
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/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
#include "ARMCM4.h"
#elif defined (ARMCM4_FP)
#include "ARMCM4_FP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

85
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/ARMCM55_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/* memory regions are:
secure ROM: 0x10000000
non-secure ROM: 0x00000000
secure RAM: 0x30000000
non-secure RAM: 0x20000000
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
; *(Veneer$$CMSE) ; uncomment for secure applications
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

154
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/startup_ARMCM55.c Normal file
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/******************************************************************************
* @file startup_ARMCM55.c
* @brief CMSIS Core Device Startup File for ARMCM55 Device
* @version V1.0.0
* @date 31. March 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM55)
#include "ARMCM55.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
SecureFault_Handler, /* -9 Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 480 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif

90
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/system_ARMCM55.c Normal file
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/**************************************************************************//**
* @file system_ARMCM55.c
* @brief CMSIS Device System Source File for
* ARMCM55 Device
* @version V1.0.0
* @date 23. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM55)
#include "ARMCM55.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM55.h"
#endif
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL ( 5000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (5U * XTAL)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
#endif
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

76
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct Normal file
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@@ -0,0 +1,76 @@
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

143
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/******************************************************************************
* @file startup_ARMCM7.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM7)
#include "ARMCM7.h"
#elif defined (ARMCM7_SP)
#include "ARMCM7_SP.h"
#elif defined (ARMCM7_DP)
#include "ARMCM7_DP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
__NO_RETURN void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

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/**************************************************************************//**
* @file system_ARMCM7.c
* @brief CMSIS Device System Source File for
* ARMCM7 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM7)
#include "ARMCM7.h"
#elif defined (ARMCM7_SP)
#include "ARMCM7_SP.h"
#elif defined (ARMCM7_DP)
#include "ARMCM7_DP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

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/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions
The file can be executed in the following way:
1) manually from uVision command window (in debug mode) using command:
INCLUIDE arm_class_marks_example.ini
*/
// usual initialisation for target setup
MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash
MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM

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reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/arm_bayes_example_f32.c Normal file
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/* ----------------------------------------------------------------------
* Copyright (C) 2019-2020 ARM Limited. All rights reserved.
*
* $Date: 09. December 2019
* $Revision: V1.0.0
*
* Project: CMSIS DSP Library
* Title: arm_bayes_example_f32.c
*
* Description: Example code demonstrating how to use Bayes functions.
*
* Target Processor: Cortex-M/Cortex-A
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
/**
* @ingroup groupExamples
*/
/**
* @defgroup BayesExample Bayes Example
*
* \par Description:
* \par
* Demonstrates the use of Bayesian classifier functions. It is complementing the tutorial
* about classical ML with CMSIS-DSP and python scikit-learn:
* https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/implement-classical-ml-with-arm-cmsis-dsp-libraries
*
*/
/** \example arm_bayes_example_f32.c
*/
#include <math.h>
#include <stdio.h>
#include "arm_math.h"
/*
Those parameters can be generated with the python library scikit-learn.
*/
arm_gaussian_naive_bayes_instance_f32 S;
#define NB_OF_CLASSES 3
#define VECTOR_DIMENSION 2
const float32_t theta[NB_OF_CLASSES*VECTOR_DIMENSION] = {
1.4539529436590528f, 0.8722776016801852f,
-1.5267934452462473f, 0.903204577814203f,
-0.15338006360932258f, -2.9997913665803964f
}; /**< Mean values for the Gaussians */
const float32_t sigma[NB_OF_CLASSES*VECTOR_DIMENSION] = {
1.0063470889514925f, 0.9038018246524426f,
1.0224479953244736f, 0.7768764290432544f,
1.1217662403241206f, 1.2303890106020325f
}; /**< Variances for the Gaussians */
const float32_t classPriors[NB_OF_CLASSES] = {
0.3333333333333333f, 0.3333333333333333f, 0.3333333333333333f
}; /**< Class prior probabilities */
int32_t main(void)
{
/* Array of input data */
float32_t in[2];
/* Result of the classifier */
float32_t result[NB_OF_CLASSES];
float32_t temp[NB_OF_CLASSES];
float32_t maxProba;
uint32_t index;
S.vectorDimension = VECTOR_DIMENSION;
S.numberOfClasses = NB_OF_CLASSES;
S.theta = theta;
S.sigma = sigma;
S.classPriors = classPriors;
S.epsilon=4.328939296523643e-09f;
in[0] = 1.5f;
in[1] = 1.0f;
index = arm_gaussian_naive_bayes_predict_f32(&S, in, result,temp);
maxProba = result[index];
#if defined(SEMIHOSTING)
printf("Class = %d\n", index);
#endif
in[0] = -1.5f;
in[1] = 1.0f;
index = arm_gaussian_naive_bayes_predict_f32(&S, in, result,temp);
maxProba = result[index];
#if defined(SEMIHOSTING)
printf("Class = %d\n", index);
#endif
in[0] = 0.0f;
in[1] = -3.0f;
index = arm_gaussian_naive_bayes_predict_f32(&S, in, result,temp);
maxProba = result[index];
#if defined(SEMIHOSTING)
printf("Class = %d\n", index);
#endif
#if !defined(SEMIHOSTING)
while (1); /* main function does not return */
#endif
}

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from sklearn.naive_bayes import GaussianNB
import random
import numpy as np
import math
from pylab import scatter,figure, clf, plot, xlabel, ylabel, xlim, ylim, title, grid, axes, show,semilogx, semilogy
import matplotlib.pyplot as plt
from matplotlib.font_manager import FontProperties
# Generation of data to train the classifier
# 100 vectors are generated. Vector have dimension 2 so can be represented as points
NBVECS = 100
VECDIM = 2
# 3 cluster of points are generated
ballRadius = 1.0
x1 = [1.5, 1] + ballRadius * np.random.randn(NBVECS,VECDIM)
x2 = [-1.5, 1] + ballRadius * np.random.randn(NBVECS,VECDIM)
x3 = [0, -3] + ballRadius * np.random.randn(NBVECS,VECDIM)
# All points are concatenated
X_train=np.concatenate((x1,x2,x3))
# The classes are 0,1 and 2.
Y_train=np.concatenate((np.zeros(NBVECS),np.ones(NBVECS),2*np.ones(NBVECS)))
gnb = GaussianNB()
gnb.fit(X_train, Y_train)
print("Testing")
y_pred = gnb.predict([[1.5,1.0]])
print(y_pred)
y_pred = gnb.predict([[-1.5,1.0]])
print(y_pred)
y_pred = gnb.predict([[0,-3.0]])
print(y_pred)
# Dump of data for CMSIS-DSP
print("Parameters")
# Gaussian averages
print("Theta = ",list(np.reshape(gnb.theta_,np.size(gnb.theta_))))
# Gaussian variances
print("Sigma = ",list(np.reshape(gnb.sigma_,np.size(gnb.sigma_))))
# Class priors
print("Prior = ",list(np.reshape(gnb.class_prior_,np.size(gnb.class_prior_))))
print("Epsilon = ",gnb.epsilon_)
# Some bounds are computed for the graphical representation
x_min = X_train[:, 0].min()
x_max = X_train[:, 0].max()
y_min = X_train[:, 1].min()
y_max = X_train[:, 1].max()
font = FontProperties()
font.set_size(20)
r=plt.figure()
plt.axis('off')
plt.text(1.5,1.0,"A", verticalalignment='center', horizontalalignment='center',fontproperties=font)
plt.text(-1.5,1.0,"B",verticalalignment='center', horizontalalignment='center', fontproperties=font)
plt.text(0,-3,"C", verticalalignment='center', horizontalalignment='center',fontproperties=font)
scatter(x1[:,0],x1[:,1],s=1.0,color='#FF6B00')
scatter(x2[:,0],x2[:,1],s=1.0,color='#95D600')
scatter(x3[:,0],x3[:,1],s=1.0,color='#00C1DE')
#r.savefig('fig.jpeg')
#plt.close(r)
show()

8
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
#------------------------------------------------------------------------------

8
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
#------------------------------------------------------------------------------

9
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
#------------------------------------------------------------------------------

25
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM55_FP_MVE_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU)
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
#
cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU)
cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
#------------------------------------------------------------------------------

9
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM7_SP_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
#------------------------------------------------------------------------------

10
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt Normal file
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CMSIS DSP_Lib example arm_class_marks_example
The example is available for different targets:
Cortex-M0
Cortex-M3
Cortex-M4 with FPU
Cortex-M7 with single precision FPU
Cortex-M55 with double precision FPU, Integer + Floating Point MVE
The example is configured for Models Debugger

45
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/CMakeLists.txt Normal file
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cmake_minimum_required (VERSION 3.14)
project (arm_class_marks_example VERSION 0.1)
# Needed to include the configBoot module
# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake)
set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..)
set(DSP ${ROOT}/CMSIS/DSP)
# Add DSP folder to module path
list(APPEND CMAKE_MODULE_PATH ${DSP})
###################################
#
# LIBRARIES
#
###################################
###########
#
# CMSIS DSP
#
add_subdirectory(../../../Source bin_dsp)
###################################
#
# TEST APPLICATION
#
###################################
add_executable(arm_class_marks_example)
include(config)
configApp(arm_class_marks_example ${ROOT})
target_sources(arm_class_marks_example PRIVATE arm_class_marks_example_f32.c)
### Sources and libs
target_link_libraries(arm_class_marks_example PRIVATE CMSISDSP)

76
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/ARMCM0_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

131
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.c Normal file
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/******************************************************************************
* @file startup_ARMCM0.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM0.h"
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10..31 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

56
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c Normal file
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/**************************************************************************//**
* @file system_ARMCM0.c
* @brief CMSIS Device System Source File for
* ARMCM0 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM0.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}

76
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/ARMCM3_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

135
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.c Normal file
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@@ -0,0 +1,135 @@
/******************************************************************************
* @file startup_ARMCM3.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM3.h"
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void) ;
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
__NO_RETURN void Default_Handler(void);
__NO_RETURN void Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
__NO_RETURN void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

65
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c Normal file
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/**************************************************************************//**
* @file system_ARMCM3.c
* @brief CMSIS Device System Source File for
* ARMCM3 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM3.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

76
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

141
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c Normal file
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@@ -0,0 +1,141 @@
/******************************************************************************
* @file startup_ARMCM4.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
#include "ARMCM4.h"
#elif defined (ARMCM4_FP)
#include "ARMCM4_FP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
__NO_RETURN void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

81
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c Normal file
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@@ -0,0 +1,81 @@
/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
#include "ARMCM4.h"
#elif defined (ARMCM4_FP)
#include "ARMCM4_FP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

85
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/* memory regions are:
secure ROM: 0x10000000
non-secure ROM: 0x00000000
secure RAM: 0x30000000
non-secure RAM: 0x20000000
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
; *(Veneer$$CMSE) ; uncomment for secure applications
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

154
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/******************************************************************************
* @file startup_ARMCM55.c
* @brief CMSIS Core Device Startup File for ARMCM55 Device
* @version V1.0.0
* @date 31. March 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM55)
#include "ARMCM55.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
SecureFault_Handler, /* -9 Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 480 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif

90
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/**************************************************************************//**
* @file system_ARMCM55.c
* @brief CMSIS Device System Source File for
* ARMCM55 Device
* @version V1.0.0
* @date 23. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM55)
#include "ARMCM55.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM55.h"
#endif
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL ( 5000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (5U * XTAL)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
#endif
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

76
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

143
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c Normal file
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/******************************************************************************
* @file startup_ARMCM7.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM7)
#include "ARMCM7.h"
#elif defined (ARMCM7_SP)
#include "ARMCM7_SP.h"
#elif defined (ARMCM7_DP)
#include "ARMCM7_DP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
__NO_RETURN void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

83
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c Normal file
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/**************************************************************************//**
* @file system_ARMCM7.c
* @brief CMSIS Device System Source File for
* ARMCM7 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM7)
#include "ARMCM7.h"
#elif defined (ARMCM7_SP)
#include "ARMCM7_SP.h"
#elif defined (ARMCM7_DP)
#include "ARMCM7_DP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

15
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example.ini Normal file
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/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions
The file can be executed in the following way:
1) manually from uVision command window (in debug mode) using command:
INCLUIDE arm_class_marks_example.ini
*/
// usual initialisation for target setup
MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash
MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM

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reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c Normal file
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.0
*
* Project: CMSIS DSP Library
* Title: arm_class_marks_example_f32.c
*
* Description: Example code to calculate Minimum, Maximum
* Mean, std and variance of marks obtained in a class
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
/**
* @ingroup groupExamples
*/
/**
* @defgroup ClassMarks Class Marks Example
*
* \par Description:
* \par
* Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance
* and Matrix functions to calculate statistical values of marks obtained in a class.
*
* \note This example also demonstrates the usage of static initialization.
*
* \par Variables Description:
* \par
* \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects
* \li \c max_marks Maximum of all marks
* \li \c min_marks Minimum of all marks
* \li \c mean Mean of all marks
* \li \c var Variance of the marks
* \li \c std Standard deviation of the marks
* \li \c numStudents Total number of students in the class
*
* \par CMSIS DSP Software Library Functions Used:
* \par
* - arm_mat_init_f32()
* - arm_mat_mult_f32()
* - arm_max_f32()
* - arm_min_f32()
* - arm_mean_f32()
* - arm_std_f32()
* - arm_var_f32()
*
* <b> Refer </b>
* \link arm_class_marks_example_f32.c \endlink
*
*/
/** \example arm_class_marks_example_f32.c
*/
#include "arm_math.h"
#if defined(SEMIHOSTING)
#include <stdio.h>
#endif
#define USE_STATIC_INIT
/* ----------------------------------------------------------------------
** Global defines
** ------------------------------------------------------------------- */
#define TEST_LENGTH_SAMPLES (20*4)
/* ----------------------------------------------------------------------
** List of Marks scored by 20 students for 4 subjects
** ------------------------------------------------------------------- */
const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] =
{
42.000000, 37.000000, 81.000000, 28.000000,
83.000000, 72.000000, 36.000000, 38.000000,
32.000000, 51.000000, 63.000000, 64.000000,
97.000000, 82.000000, 95.000000, 90.000000,
66.000000, 51.000000, 54.000000, 42.000000,
67.000000, 56.000000, 45.000000, 57.000000,
67.000000, 69.000000, 35.000000, 52.000000,
29.000000, 81.000000, 58.000000, 47.000000,
38.000000, 76.000000, 100.000000, 29.000000,
33.000000, 47.000000, 29.000000, 50.000000,
34.000000, 41.000000, 61.000000, 46.000000,
52.000000, 50.000000, 48.000000, 36.000000,
47.000000, 55.000000, 44.000000, 40.000000,
100.000000, 94.000000, 84.000000, 37.000000,
32.000000, 71.000000, 47.000000, 77.000000,
31.000000, 50.000000, 49.000000, 35.000000,
63.000000, 67.000000, 40.000000, 31.000000,
29.000000, 68.000000, 61.000000, 38.000000,
31.000000, 28.000000, 28.000000, 76.000000,
55.000000, 33.000000, 29.000000, 39.000000
};
/* ----------------------------------------------------------------------
* Number of subjects X 1
* ------------------------------------------------------------------- */
const float32_t testUnity_f32[4] =
{
1.000, 1.000, 1.000, 1.000
};
/* ----------------------------------------------------------------------
** f32 Output buffer
** ------------------------------------------------------------------- */
static float32_t testOutput[TEST_LENGTH_SAMPLES];
/* ------------------------------------------------------------------
* Global defines
*------------------------------------------------------------------- */
#define NUMSTUDENTS 20
#define NUMSUBJECTS 4
/* ------------------------------------------------------------------
* Global variables
*------------------------------------------------------------------- */
uint32_t numStudents = 20;
uint32_t numSubjects = 4;
float32_t max_marks, min_marks, mean, std, var;
uint32_t student_num;
/* ----------------------------------------------------------------------------------
* Main f32 test function. It returns maximum marks secured and student number
* ------------------------------------------------------------------------------- */
int32_t main()
{
#ifndef USE_STATIC_INIT
arm_matrix_instance_f32 srcA;
arm_matrix_instance_f32 srcB;
arm_matrix_instance_f32 dstC;
/* Input and output matrices initializations */
arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32);
arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32);
arm_mat_init_f32(&dstC, numStudents, 1, testOutput);
#else
/* Static Initializations of Input and output matrix sizes and array */
arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32};
arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32};
arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput};
#endif
/* ----------------------------------------------------------------------
*Call the Matrix multiplication process function
* ------------------------------------------------------------------- */
arm_mat_mult_f32(&srcA, &srcB, &dstC);
/* ----------------------------------------------------------------------
** Call the Max function to calculate max marks among numStudents
** ------------------------------------------------------------------- */
arm_max_f32(testOutput, numStudents, &max_marks, &student_num);
/* ----------------------------------------------------------------------
** Call the Min function to calculate min marks among numStudents
** ------------------------------------------------------------------- */
arm_min_f32(testOutput, numStudents, &min_marks, &student_num);
/* ----------------------------------------------------------------------
** Call the Mean function to calculate mean
** ------------------------------------------------------------------- */
arm_mean_f32(testOutput, numStudents, &mean);
/* ----------------------------------------------------------------------
** Call the std function to calculate standard deviation
** ------------------------------------------------------------------- */
arm_std_f32(testOutput, numStudents, &std);
/* ----------------------------------------------------------------------
** Call the var function to calculate variance
** ------------------------------------------------------------------- */
arm_var_f32(testOutput, numStudents, &var);
#if defined(SEMIHOSTING)
printf("mean = %f, std = %f\n",mean,std);
#endif
#if !defined(SEMIHOSTING)
while (1); /* main function does not return */
#endif
}

8
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
#------------------------------------------------------------------------------

8
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
#------------------------------------------------------------------------------

9
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
#------------------------------------------------------------------------------

25
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM55_FP_MVE_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU)
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
#
cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU)
cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
#------------------------------------------------------------------------------

9
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
#------------------------------------------------------------------------------

10
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CMSIS DSP_Lib example arm_convolution_example.
The example is available for different targets:
Cortex-M0
Cortex-M3
Cortex-M4 with FPU
Cortex-M7 with single precision FPU
Cortex-M55 with double precision FPU, Integer + Floating Point MVE
The example is configured for Models Debugger

45
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cmake_minimum_required (VERSION 3.14)
project (arm_convolution_example VERSION 0.1)
# Needed to include the configBoot module
# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake)
set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..)
set(DSP ${ROOT}/CMSIS/DSP)
# Add DSP folder to module path
list(APPEND CMAKE_MODULE_PATH ${DSP})
###################################
#
# LIBRARIES
#
###################################
###########
#
# CMSIS DSP
#
add_subdirectory(../../../Source bin_dsp)
###################################
#
# TEST APPLICATION
#
###################################
add_executable(arm_convolution_example)
include(config)
configApp(arm_convolution_example ${ROOT})
target_sources(arm_convolution_example PRIVATE arm_convolution_example_f32.c math_helper.c)
### Sources and libs
target_link_libraries(arm_convolution_example PRIVATE CMSISDSP)

76
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

131
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/******************************************************************************
* @file startup_ARMCM0.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM0.h"
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10..31 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

56
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/**************************************************************************//**
* @file system_ARMCM0.c
* @brief CMSIS Device System Source File for
* ARMCM0 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM0.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}

76
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

135
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/******************************************************************************
* @file startup_ARMCM3.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM3.h"
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void) ;
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
__NO_RETURN void Default_Handler(void);
__NO_RETURN void Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
__NO_RETURN void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

65
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/**************************************************************************//**
* @file system_ARMCM3.c
* @brief CMSIS Device System Source File for
* ARMCM3 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM3.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

76
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

141
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c Normal file
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/******************************************************************************
* @file startup_ARMCM4.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
#include "ARMCM4.h"
#elif defined (ARMCM4_FP)
#include "ARMCM4_FP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
__NO_RETURN void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

81
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c Normal file
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/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
#include "ARMCM4.h"
#elif defined (ARMCM4_FP)
#include "ARMCM4_FP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

85
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/ARMCM55_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/* memory regions are:
secure ROM: 0x10000000
non-secure ROM: 0x00000000
secure RAM: 0x30000000
non-secure RAM: 0x20000000
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
; *(Veneer$$CMSE) ; uncomment for secure applications
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

154
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/******************************************************************************
* @file startup_ARMCM55.c
* @brief CMSIS Core Device Startup File for ARMCM55 Device
* @version V1.0.0
* @date 31. March 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM55)
#include "ARMCM55.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
SecureFault_Handler, /* -9 Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 480 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif

90
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/system_ARMCM55.c Normal file
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/**************************************************************************//**
* @file system_ARMCM55.c
* @brief CMSIS Device System Source File for
* ARMCM55 Device
* @version V1.0.0
* @date 23. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM55)
#include "ARMCM55.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM55.h"
#endif
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL ( 5000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (5U * XTAL)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
#endif
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

76
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

143
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/******************************************************************************
* @file startup_ARMCM7.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM7)
#include "ARMCM7.h"
#elif defined (ARMCM7_SP)
#include "ARMCM7_SP.h"
#elif defined (ARMCM7_DP)
#include "ARMCM7_DP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
__NO_RETURN void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

83
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/**************************************************************************//**
* @file system_ARMCM7.c
* @brief CMSIS Device System Source File for
* ARMCM7 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM7)
#include "ARMCM7.h"
#elif defined (ARMCM7_SP)
#include "ARMCM7_SP.h"
#elif defined (ARMCM7_DP)
#include "ARMCM7_DP.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

15
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/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions
The file can be executed in the following way:
1) manually from uVision command window (in debug mode) using command:
INCLUIDE arm_convolution_example.ini
*/
// usual initialisation for target setup
MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash
MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM

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reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c Normal file
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.0
*
* Project: CMSIS DSP Library
* Title: arm_convolution_example_f32.c
*
* Description: Example code demonstrating Convolution of two input signals using fft.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
/**
* @ingroup groupExamples
*/
/**
* @defgroup ConvolutionExample Convolution Example
*
* \par Description:
* \par
* Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex
* Multiplication, and Support Functions.
*
* \par Algorithm:
* \par
* The convolution theorem states that convolution in the time domain corresponds to
* multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of
* two signals is equal to the product of their individual Fourier transforms.
* The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT).
* \par
* Two input signals, <code>a[n]</code> and <code>b[n]</code>, with lengths \c n1 and \c n2 respectively,
* are zero padded so that their lengths become \c N, which is greater than or equal to <code>(n1+n2-1)</code>
* and is a power of 4 as FFT implementation is radix-4.
* The convolution of <code>a[n]</code> and <code>b[n]</code> is obtained by taking the FFT of the input
* signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of
* the multiplied result.
* \par
* This is denoted by the following equations:
* <pre> A[k] = FFT(a[n],N)
* B[k] = FFT(b[n],N)
* conv(a[n], b[n]) = IFFT(A[k] * B[k], N)</pre>
* where <code>A[k]</code> and <code>B[k]</code> are the N-point FFTs of the signals <code>a[n]</code>
* and <code>b[n]</code> respectively.
* The length of the convolved signal is <code>(n1+n2-1)</code>.
*
* \par Block Diagram:
* \par
* \image html Convolution.gif
*
* \par Variables Description:
* \par
* \li \c testInputA_f32 points to the first input sequence
* \li \c srcALen length of the first input sequence
* \li \c testInputB_f32 points to the second input sequence
* \li \c srcBLen length of the second input sequence
* \li \c outLen length of convolution output sequence, <code>(srcALen + srcBLen - 1)</code>
* \li \c AxB points to the output array where the product of individual FFTs of inputs is stored.
*
* \par CMSIS DSP Software Library Functions Used:
* \par
* - arm_fill_f32()
* - arm_copy_f32()
* - arm_cfft_radix4_init_f32()
* - arm_cfft_radix4_f32()
* - arm_cmplx_mult_cmplx_f32()
*
* <b> Refer </b>
* \link arm_convolution_example_f32.c \endlink
*
*/
/** \example arm_convolution_example_f32.c
*/
#include "arm_math.h"
#include "math_helper.h"
#if defined(SEMIHOSTING)
#include <stdio.h>
#endif
/* ----------------------------------------------------------------------
* Defines each of the tests performed
* ------------------------------------------------------------------- */
#define MAX_BLOCKSIZE 128
#define DELTA (0.000001f)
#define SNR_THRESHOLD 90
/* ----------------------------------------------------------------------
* Declare I/O buffers
* ------------------------------------------------------------------- */
float32_t Ak[MAX_BLOCKSIZE]; /* Input A */
float32_t Bk[MAX_BLOCKSIZE]; /* Input B */
float32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */
/* ----------------------------------------------------------------------
* Test input data for Floating point Convolution example for 32-blockSize
* Generated by the MATLAB randn() function
* ------------------------------------------------------------------- */
float32_t testInputA_f32[64] =
{
-0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285,
1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579,
-0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377,
-2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827,
-0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938,
-0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619,
0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222,
-0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249,
-1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355,
-1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090,
-0.161050, -0.940794, 0.367961, 0.291907
};
float32_t testInputB_f32[64] =
{
0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885,
0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493,
-0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692,
-0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962,
0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397,
1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399,
-1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011,
0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456,
0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182,
-1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952,
0.635474, -0.970468, 1.334057, -0.111370
};
const float testRefOutput_f32[127] =
{
-0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656,
5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012,
-1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236,
-7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508,
-1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267,
11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552,
1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344,
-0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488,
-13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415,
-0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462,
8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280,
7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073,
-2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291,
1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885,
8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417,
8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678,
-6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410,
-2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013,
-3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358,
-4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638,
1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440, 0
};
/* ----------------------------------------------------------------------
* Declare Global variables
* ------------------------------------------------------------------- */
uint32_t srcALen = 64; /* Length of Input A */
uint32_t srcBLen = 64; /* Length of Input B */
uint32_t outLen; /* Length of convolution output */
float32_t snr; /* output SNR */
int32_t main(void)
{
arm_status status; /* Status of the example */
arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */
#if defined(SEMIHOSTING)
printf("START\n");
#endif
/* CFFT Structure instance pointer */
arm_cfft_radix4_instance_f32 *cfft_instance_ptr =
(arm_cfft_radix4_instance_f32*) &cfft_instance;
/* output length of convolution */
outLen = srcALen + srcBLen - 1;
/* Initialise the fft input buffers with all zeros */
arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE);
arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE);
/* Copy the input values to the fft input buffers */
arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2);
arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2);
/* Initialize the CFFT function to compute 64 point fft */
status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1);
/* Transform input a[n] from time domain to frequency domain A[k] */
arm_cfft_radix4_f32(cfft_instance_ptr, Ak);
/* Transform input b[n] from time domain to frequency domain B[k] */
arm_cfft_radix4_f32(cfft_instance_ptr, Bk);
/* Complex Multiplication of the two input buffers in frequency domain */
arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2);
/* Initialize the CIFFT function to compute 64 point ifft */
status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1);
/* Transform the multiplication output from frequency domain to time domain,
that gives the convolved output. */
arm_cfft_radix4_f32(cfft_instance_ptr, AxB);
/* SNR Calculation */
snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1);
/* Compare the SNR with threshold to test whether the
computed output is matched with the reference output values. */
status = (snr <= SNR_THRESHOLD) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS;
if (status != ARM_MATH_SUCCESS)
{
#if defined (SEMIHOSTING)
printf("FAILURE\n");
#else
while (1); /* main function does not return */
#endif
}
else
{
#if defined (SEMIHOSTING)
printf("SUCCESS\n");
#else
while (1); /* main function does not return */
#endif
}
}
/** \endlink */

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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.0 b
*
* Project: CMSIS DSP Library
*
* Title: math_helper.c
*
* Description: Definition of all helper functions required.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
/* ----------------------------------------------------------------------
* Include standard header files
* -------------------------------------------------------------------- */
#include<math.h>
/* ----------------------------------------------------------------------
* Include project header files
* -------------------------------------------------------------------- */
#include "math_helper.h"
/**
* @brief Caluclation of SNR
* @param[in] pRef Pointer to the reference buffer
* @param[in] pTest Pointer to the test buffer
* @param[in] buffSize total number of samples
* @return SNR
* The function Caluclates signal to noise ratio for the reference output
* and test output
*/
float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
{
float EnergySignal = 0.0, EnergyError = 0.0;
uint32_t i;
float SNR;
int temp;
int *test;
for (i = 0; i < buffSize; i++)
{
/* Checking for a NAN value in pRef array */
test = (int *)(&pRef[i]);
temp = *test;
if (temp == 0x7FC00000)
{
return(0);
}
/* Checking for a NAN value in pTest array */
test = (int *)(&pTest[i]);
temp = *test;
if (temp == 0x7FC00000)
{
return(0);
}
EnergySignal += pRef[i] * pRef[i];
EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
}
/* Checking for a NAN value in EnergyError */
test = (int *)(&EnergyError);
temp = *test;
if (temp == 0x7FC00000)
{
return(0);
}
SNR = 10 * log10 (EnergySignal / EnergyError);
return (SNR);
}
/**
* @brief Provide guard bits for Input buffer
* @param[in,out] input_buf Pointer to input buffer
* @param[in] blockSize block Size
* @param[in] guard_bits guard bits
* @return none
* The function Provides the guard bits for the buffer
* to avoid overflow
*/
void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
uint32_t guard_bits)
{
uint32_t i;
for (i = 0; i < blockSize; i++)
{
input_buf[i] = input_buf[i] >> guard_bits;
}
}
/**
* @brief Converts float to fixed in q12.20 format
* @param[in] pIn pointer to input buffer
* @param[out] pOut pointer to outputbuffer
* @param[in] numSamples number of samples in the input buffer
* @return none
* The function converts floating point values to fixed point(q12.20) values
*/
void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
{
uint32_t i;
for (i = 0; i < numSamples; i++)
{
/* 1048576.0f corresponds to pow(2, 20) */
pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
if (pIn[i] == (float) 1.0)
{
pOut[i] = 0x000FFFFF;
}
}
}
/**
* @brief Compare MATLAB Reference Output and ARM Test output
* @param[in] pIn Pointer to Ref buffer
* @param[in] pOut Pointer to Test buffer
* @param[in] numSamples number of samples in the buffer
* @return maximum difference
*/
uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples)
{
uint32_t i;
int32_t diff, diffCrnt = 0;
uint32_t maxDiff = 0;
for (i = 0; i < numSamples; i++)
{
diff = pIn[i] - pOut[i];
diffCrnt = (diff > 0) ? diff : -diff;
if (diffCrnt > maxDiff)
{
maxDiff = diffCrnt;
}
}
return(maxDiff);
}
/**
* @brief Compare MATLAB Reference Output and ARM Test output
* @param[in] pIn Pointer to Ref buffer
* @param[in] pOut Pointer to Test buffer
* @param[in] numSamples number of samples in the buffer
* @return maximum difference
*/
uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
{
uint32_t i;
int32_t diff, diffCrnt = 0;
uint32_t maxDiff = 0;
for (i = 0; i < numSamples; i++)
{
diff = pIn[i] - pOut[i];
diffCrnt = (diff > 0) ? diff : -diff;
if (diffCrnt > maxDiff)
{
maxDiff = diffCrnt;
}
}
return(maxDiff);
}
/**
* @brief Provide guard bits for Input buffer
* @param[in,out] input_buf Pointer to input buffer
* @param[in] blockSize block Size
* @param[in] guard_bits guard bits
* @return none
* The function Provides the guard bits for the buffer
* to avoid overflow
*/
void arm_provide_guard_bits_q31 (q31_t * input_buf,
uint32_t blockSize,
uint32_t guard_bits)
{
uint32_t i;
for (i = 0; i < blockSize; i++)
{
input_buf[i] = input_buf[i] >> guard_bits;
}
}
/**
* @brief Provide guard bits for Input buffer
* @param[in,out] input_buf Pointer to input buffer
* @param[in] blockSize block Size
* @param[in] guard_bits guard bits
* @return none
* The function Provides the guard bits for the buffer
* to avoid overflow
*/
void arm_provide_guard_bits_q7 (q7_t * input_buf,
uint32_t blockSize,
uint32_t guard_bits)
{
uint32_t i;
for (i = 0; i < blockSize; i++)
{
input_buf[i] = input_buf[i] >> guard_bits;
}
}
/**
* @brief Caluclates number of guard bits
* @param[in] num_adds number of additions
* @return guard bits
* The function Caluclates the number of guard bits
* depending on the numtaps
*/
uint32_t arm_calc_guard_bits (uint32_t num_adds)
{
uint32_t i = 1, j = 0;
if (num_adds == 1)
{
return (0);
}
while (i < num_adds)
{
i = i * 2;
j++;
}
return (j);
}
/**
* @brief Apply guard bits to buffer
* @param[in,out] pIn pointer to input buffer
* @param[in] numSamples number of samples in the input buffer
* @param[in] guard_bits guard bits
* @return none
*/
void arm_apply_guard_bits (float32_t *pIn,
uint32_t numSamples,
uint32_t guard_bits)
{
uint32_t i;
for (i = 0; i < numSamples; i++)
{
pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
}
}
/**
* @brief Calculates pow(2, numShifts)
* @param[in] numShifts number of shifts
* @return pow(2, numShifts)
*/
uint32_t arm_calc_2pow(uint32_t numShifts)
{
uint32_t i, val = 1;
for (i = 0; i < numShifts; i++)
{
val = val * 2;
}
return(val);
}
/**
* @brief Converts float to fixed q14
* @param[in] pIn pointer to input buffer
* @param[out] pOut pointer to output buffer
* @param[in] numSamples number of samples in the buffer
* @return none
* The function converts floating point values to fixed point values
*/
void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
{
uint32_t i;
for (i = 0; i < numSamples; i++)
{
/* 16384.0f corresponds to pow(2, 14) */
pOut[i] = (q15_t) (pIn[i] * 16384.0f);
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
if (pIn[i] == (float) 2.0)
{
pOut[i] = 0x7FFF;
}
}
}
/**
* @brief Converts float to fixed q30 format
* @param[in] pIn pointer to input buffer
* @param[out] pOut pointer to output buffer
* @param[in] numSamples number of samples in the buffer
* @return none
* The function converts floating point values to fixed point values
*/
void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples)
{
uint32_t i;
for (i = 0; i < numSamples; i++)
{
/* 1073741824.0f corresponds to pow(2, 30) */
pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
if (pIn[i] == (float) 2.0)
{
pOut[i] = 0x7FFFFFFF;
}
}
}
/**
* @brief Converts float to fixed q30 format
* @param[in] pIn pointer to input buffer
* @param[out] pOut pointer to output buffer
* @param[in] numSamples number of samples in the buffer
* @return none
* The function converts floating point values to fixed point values
*/
void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
{
uint32_t i;
for (i = 0; i < numSamples; i++)
{
/* 1073741824.0f corresponds to pow(2, 30) */
pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
if (pIn[i] == (float) 4.0)
{
pOut[i] = 0x7FFFFFFF;
}
}
}
/**
* @brief Converts float to fixed q28 format
* @param[in] pIn pointer to input buffer
* @param[out] pOut pointer to output buffer
* @param[in] numSamples number of samples in the buffer
* @return none
* The function converts floating point values to fixed point values
*/
void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
{
uint32_t i;
for (i = 0; i < numSamples; i++)
{
/* 268435456.0f corresponds to pow(2, 28) */
pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
if (pIn[i] == (float) 8.0)
{
pOut[i] = 0x7FFFFFFF;
}
}
}
/*
Conflicting with the new clip functions in CMSIS-DSP and not used
in the examples.
*/
#if 0
/**
* @brief Clip the float values to +/- 1
* @param[in,out] pIn input buffer
* @param[in] numSamples number of samples in the buffer
* @return none
* The function converts floating point values to fixed point values
*/
void arm_clip_f32 (float *pIn, uint32_t numSamples)
{
uint32_t i;
for (i = 0; i < numSamples; i++)
{
if (pIn[i] > 1.0f)
{
pIn[i] = 1.0;
}
else if ( pIn[i] < -1.0f)
{
pIn[i] = -1.0;
}
}
}
#endif

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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.0
*
* Project: CMSIS DSP Library
*
* Title: math_helper.h
*
* Description: Prototypes of all helper functions required.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#include "arm_math.h"
#ifndef MATH_HELPER_H
#define MATH_HELPER_H
float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
uint32_t arm_calc_guard_bits(uint32_t num_adds);
void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
uint32_t arm_calc_2pow(uint32_t guard_bits);
#endif

8
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM0_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
#------------------------------------------------------------------------------

8
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
#------------------------------------------------------------------------------

9
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
#------------------------------------------------------------------------------

25
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM55_FP_MVE_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU)
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
#
cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU)
cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
#------------------------------------------------------------------------------

9
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM7_SP_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction)
armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction)
armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
#------------------------------------------------------------------------------

10
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt Normal file
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CMSIS DSP_Lib example arm_dotproduct_example.
The example is available for different targets:
Cortex-M0
Cortex-M3
Cortex-M4 with FPU
Cortex-M7 with single precision FPU
Cortex-M55 with double precision FPU, Integer + Floating Point MVE
The example is configured for Models Debugger

45
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/CMakeLists.txt Normal file
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cmake_minimum_required (VERSION 3.14)
project (arm_dotproduct_example VERSION 0.1)
# Needed to include the configBoot module
# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake)
set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..)
set(DSP ${ROOT}/CMSIS/DSP)
# Add DSP folder to module path
list(APPEND CMAKE_MODULE_PATH ${DSP})
###################################
#
# LIBRARIES
#
###################################
###########
#
# CMSIS DSP
#
add_subdirectory(../../../Source bin_dsp)
###################################
#
# TEST APPLICATION
#
###################################
add_executable(arm_dotproduct_example)
include(config)
configApp(arm_dotproduct_example ${ROOT})
target_sources(arm_dotproduct_example PRIVATE arm_dotproduct_example_f32.c)
### Sources and libs
target_link_libraries(arm_dotproduct_example PRIVATE CMSISDSP)

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reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/ARMCM0_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

131
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.c Normal file
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@@ -0,0 +1,131 @@
/******************************************************************************
* @file startup_ARMCM0.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM0.h"
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10..31 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

56
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c Normal file
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@@ -0,0 +1,56 @@
/**************************************************************************//**
* @file system_ARMCM0.c
* @brief CMSIS Device System Source File for
* ARMCM0 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM0.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}

76
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/ARMCM3_ac6.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

135
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.c Normal file
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@@ -0,0 +1,135 @@
/******************************************************************************
* @file startup_ARMCM3.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device
* @version V2.0.2
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM3.h"
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void) ;
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
__NO_RETURN void Default_Handler(void);
__NO_RETURN void Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
__NO_RETURN void HardFault_Handler(void)
{
while(1);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

65
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c Normal file
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@@ -0,0 +1,65 @@
/**************************************************************************//**
* @file system_ARMCM3.c
* @brief CMSIS Device System Source File for
* ARMCM3 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "ARMCM3.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

76
reader/STM32CubeExpansion_ALIRO_V1_0_0/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct Normal file
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@@ -0,0 +1,76 @@
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE __RAM_BASE
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

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