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feat(registers): NTAG5 STATUS_REG / CONFIG_REG self-describing views

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Add Ntag5StatusReg and Ntag5ConfigReg (Register subclasses) and bind
them as tag.status_reg / tag.config_reg on the NTAG 5 platform. Purely
additive: every existing per-field accessor (disable_nfc, arbiter_mode,
sram_enable, ...) stays, and the config_reg setter re-syncs the
_arbiter_mode / _sram_enabled sibling caches the per-field setters keep,
so the sim internals are untouched.

- Ntag5StatusReg (0xA0): field/VCC/boot/lock/EEPROM/SRAM status bits
- Ntag5ConfigReg (0xA1): disable_nfc, arbiter_mode (normal/mirror/
  pass-through/PHDC), sram_enable, config_pt_transfer_dir

Bit layout taken straight from the existing hand-rolled accessors, so
the register view decodes the very same bytes (cross-checked in tests).
5 new tests.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
michael
2026-07-14 08:54:24 -07:00
parent 0f597bc933
commit f8d01a9120
4 changed files with 131 additions and 4 deletions
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7
CLAUDE.md
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@@ -59,9 +59,10 @@ pm3py/
transponders/ # tag/transponder models (extracted from sim/)
bitfield.py # BitField descriptor + Register base — self-describing config/
# frame registers (T5577, EM4100, NTAG21x, Ultralight EV1/C, MFC
# access bits, NTAG I2C NC_REG/NS_REG/REG_LOCK/PT_I2C). Fields are
# documented attrs -> shell completion + repr decode table.
# Layouts cross-checked vs the firmware submodule + NXP datasheets.
# access bits, NTAG I2C NC_REG/NS_REG/REG_LOCK/PT_I2C, NTAG5
# STATUS_REG/CONFIG_REG). Fields are documented attrs -> shell
# completion + repr decode table. Layouts cross-checked vs the
# firmware submodule + NXP datasheets.
hf/iso14443a/ # Tag14443A_3/4, MifareClassic, DESFire, NfcType2/4
# nxp/type2,ntag21x,ultralight,ntag_i2c
# (NTAG210-216, Ultralight/C/EV1, NTAG I2C plus)