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Remove application-layer CRC from SRAM mailbox protocol

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ISO15693 already provides CRC-16 at the transport layer, making
the application-layer CRC redundant. Simplifies header from 6 to
4 bytes, removes crc16_continue/verify_crc, and drops STATUS_BAD_CRC.
Also updates design doc and fixes markdown table formatting.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
michael
2026-03-05 17:40:56 -08:00
parent 43cda8ac3d
commit f437e4e281
4 changed files with 45 additions and 101 deletions
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52
CLAUDE.md
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@@ -1,4 +1,4 @@
# xblink Development Guide
# xBlink Development Guide
Embedded Rust firmware for a battery-free, NFC-powered LED implant. The NTAG5Link harvests energy from an NFC field and provides EEPROM storage for LED patterns. A SAMD21E MCU reads patterns from EEPROM, programs LP5562 execution engines, then sleeps while the LP5562 autonomously drives RGBW LEDs.
@@ -24,12 +24,12 @@ cargo hf2 --release
## Dependencies
| Crate | Version | Purpose |
|-------|---------|---------|
| `xiao_m0` | 0.13 | Board support package (dev board phase) |
| `panic-halt` | 0.2 | Minimal panic handler for `no_std` |
| `cortex-m` | 0.7 | Cortex-M runtime, `critical-section-single-core` feature |
| `embedded-hal` | 1.0.0 | Hardware abstraction traits (I2C, GPIO, delay) |
| Crate | Version | Purpose |
| -------------- | ------- | -------------------------------------------------------- |
| `xiao_m0` | 0.13 | Board support package (dev board phase) |
| `panic-halt` | 0.2 | Minimal panic handler for `no_std` |
| `cortex-m` | 0.7 | Cortex-M runtime, `critical-section-single-core` feature |
| `embedded-hal` | 1.0.0 | Hardware abstraction traits (I2C, GPIO, delay) |
When porting to bare SAMD21E: replace `xiao_m0` with `atsamd-hal = { version = "0.17", features = ["samd21e"] }` and add `cortex-m-rt = "0.7"`.
@@ -68,22 +68,22 @@ The LP5562 driver does NOT enforce timing delays internally — the caller is re
Both devices share the same I2C bus (A4/A5). Non-conflicting addresses — no bus arbitration issues.
| Device | Address | Notes |
|--------|---------|-------|
| LP5562 | 0x30 | ADDR_SEL pins both low (LP5562EVM default) |
| NTAG5Link | 0x54 | Default NTP53x2 I2C slave address |
| Device | Address | Notes |
| --------- | ------- | ------------------------------------------ |
| LP5562 | 0x30 | ADDR_SEL pins both low (LP5562EVM default) |
| NTAG5Link | 0x54 | Default NTP53x2 I2C slave address |
## NTAG5Link I2C Register Map (MCU-side)
The MCU accesses NTAG5Link as a standard I2C slave — plain register read/write, NOT the NFC-side ISO15693 custom commands used by the Python ntag5sensor tooling.
| Region | Address Range | Size | Notes |
|--------|--------------|------|-------|
| Session registers | 0x00-0x06 | 7 bytes | Volatile, runtime config |
| Configuration | 0x37-0x3F | Varies | Persistent, EEPROM-backed |
| EH config | 0x3D | 1 byte | Energy harvesting voltage/current |
| SRAM | 0xF8-0xFF | 256 bytes | 64 x 4-byte blocks, volatile |
| EEPROM user memory | blocks 0x00-0x1FF | 2048 bytes | 512 x 4-byte blocks |
| Region | Address Range | Size | Notes |
| ------------------ | ----------------- | ---------- | --------------------------------- |
| Session registers | 0x00-0x06 | 7 bytes | Volatile, runtime config |
| Configuration | 0x37-0x3F | Varies | Persistent, EEPROM-backed |
| EH config | 0x3D | 1 byte | Energy harvesting voltage/current |
| SRAM | 0xF8-0xFF | 256 bytes | 64 x 4-byte blocks, volatile |
| EEPROM user memory | blocks 0x00-0x1FF | 2048 bytes | 512 x 4-byte blocks |
Key config constants (from `../ntag5sensor/vicinity/ntag5link.py`):
- `CONFIG_1_USE_CASE_CONF_I2C_SLAVE = 0 << 4` — NTAG5 as I2C slave (our mode)
@@ -93,13 +93,13 @@ Key config constants (from `../ntag5sensor/vicinity/ntag5link.py`):
## Hardware Wiring (Dev Board)
| XIAO Pin | Connection | Function |
|----------|------------|----------|
| A4 (SDA) | LP5562 SDA, NTAG5 SDA | Shared I2C data |
| A5 (SCL) | LP5562 SCL, NTAG5 SCL | Shared I2C clock |
| D0/A0 | LP5562 EN line (open-drain) | Wired-AND with hall sensor, pull-up to VCC |
| TBD (EIC) | Hall sensor output | EIC wake + wired-AND to LP5562 EN line |
| TBD (EIC) | NTAG5 FD pin | Field detect / SRAM write indication (EIC wake) |
| XIAO Pin | Connection | Function |
| --------- | --------------------------- | ----------------------------------------------- |
| A4 (SDA) | LP5562 SDA, NTAG5 SDA | Shared I2C data |
| A5 (SCL) | LP5562 SCL, NTAG5 SCL | Shared I2C clock |
| D0/A0 | LP5562 EN line (open-drain) | Wired-AND with hall sensor, pull-up to VCC |
| TBD (EIC) | Hall sensor output | EIC wake + wired-AND to LP5562 EN line |
| TBD (EIC) | NTAG5 FD pin | Field detect / SRAM write indication (EIC wake) |
**LP5562 EN wired-AND**: D0/A0 (open-drain) and hall sensor (open-drain, active-low) both connect to LP5562 EN with a 1M pull-up. Either can force EN low. Magnet kills LEDs at hardware level regardless of MCU state.
@@ -112,5 +112,5 @@ Key config constants (from `../ntag5sensor/vicinity/ntag5link.py`):
## Sibling Projects
- `../ntag5-samd21-lp562/` — Original LP5562 driver + smoke test (xblink's `src/led/lp5562.rs` is synced from here)
- `../ntag5-samd21-lp562/` — Original LP5562 driver + smoke test (xBlink's `src/led/lp5562.rs` is synced from here)
- `../ntag5sensor/` — NTAG5Link command reference (`vicinity/ntag5link.py`), I2C patterns (`vicinity/i2cbase.py`)