8dfe9117af
Implements the NFC-to-MCU SRAM mailbox protocol in src/ntag5/sram.rs: - Command parsing with CRC-16/CCITT-FALSE verification - Response building with 4-byte-aligned SRAM writes - WRITE_PATTERN: stores 112-byte pattern entries to EEPROM - GET_STATUS: returns firmware version + library summary - SET_ACTIVE: changes the active pattern index in EEPROM header - SYNC_START/SYNC_END: bulk upload with deferred header CRC - READ_LIBRARY/READ_NEXT: iterative pattern readback - MailboxState struct for cross-command state tracking Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
369 lines
13 KiB
Rust
369 lines
13 KiB
Rust
/// NTAG5Link I2C slave driver for NTP53x2.
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///
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/// Provides session register reads, EEPROM block read/write,
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/// and NDEF Type 5 text record writing.
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///
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/// I2C protocol (Section 8.3.1.4 of NTP53x2 datasheet):
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/// - READ MEMORY: write [BL_AD1, BL_AD0], read N bytes
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/// - WRITE MEMORY: write [BL_AD1, BL_AD0, D0, D1, D2, D3]
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/// - READ REGISTER: write [BL_AD1, BL_AD0, REGA], read 1 byte
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/// - WRITE REGISTER: write [BL_AD1, BL_AD0, REGA, MASK, REGDATA]
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pub mod sram;
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use embedded_hal::i2c::I2c;
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pub const DEFAULT_ADDRESS: u8 = 0x54;
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// Session register I2C block addresses (16-bit)
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pub const SESSION_CONFIG_REG: u16 = 0x10A1; // CONFIG_0_REG, CONFIG_1_REG, CONFIG_2_REG, RFU
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pub const SESSION_EH_CONFIG_REG: u16 = 0x10A7; // EH_CONFIG_REG, RFU
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pub const SESSION_I2C_SLAVE_REG: u16 = 0x10A9; // I2C_SLAVE_ADDR_REG, I2C_SLAVE_CONFIG_REG
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// SRAM I2C block address range (64 blocks × 4 bytes = 256 bytes)
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pub const SRAM_BASE_BLOCK: u16 = 0x10F8;
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pub const SRAM_BLOCK_COUNT: u16 = 64;
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pub const SRAM_SIZE: usize = 256;
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// Session register for ED/FD pin configuration
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pub const SESSION_ED_FD_PIN_CFG: u16 = 0x10A3;
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// FD pin mode: active on SRAM write by RF, cleared on I2C read
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pub const FD_MODE_SRAM_RF_WRITE: u8 = 0x04;
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// EEPROM user memory I2C block addresses
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// Block 0 = CC (capability container), blocks 1+ = NDEF data
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pub const EEPROM_BLOCK_0: u16 = 0x0000;
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// Expected config values for xblink
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// CONFIG_0: EH_MODE = low field strength (bits 3:2 = 10b)
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pub const EXPECTED_CONFIG_0: u8 = 0x08;
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// CONFIG_1: SRAM_ENABLE (bit 1) + ARBITER_MODE passthrough (bits 3:2 = 10b) + USE_CASE I2C slave (bits 5:4 = 00b)
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pub const EXPECTED_CONFIG_1: u8 = 0x0A;
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// EH_CONFIG: skip for now — EH is disabled (0x00) when powered externally.
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// Set to 0x75 (EH_ENABLE + 3.0V + 12.5mA) when running from energy harvesting.
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pub const EXPECTED_EH_CONFIG: u8 = 0x00;
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// Masks for checking — only check the bits we care about
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// CONFIG_0: bits 3:2 (EH_MODE) — ignore SRAM_COPY_EN, AUTO_STANDBY, LOCK_SESSION
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pub const CONFIG_0_MASK: u8 = 0x0C;
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// CONFIG_1: bits 5:4 (USE_CASE) + bits 3:2 (ARBITER) + bit 1 (SRAM_EN)
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pub const CONFIG_1_MASK: u8 = 0x3E;
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// EH_CONFIG: mask 0x00 — don't check EH config during external power testing
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pub const EH_CONFIG_MASK: u8 = 0x00;
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#[derive(Debug)]
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pub enum Error<E> {
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I2c(E),
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/// EEPROM write-verify failed: read-back didn't match written data
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VerifyFailed,
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}
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impl<E> From<E> for Error<E> {
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fn from(e: E) -> Self {
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Error::I2c(e)
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}
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}
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pub struct Ntag5Link<I2C> {
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i2c: I2C,
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addr: u8,
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}
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/// Config check result for a single register
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pub struct RegCheck {
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/// Register name abbreviation (e.g., "C0", "C1", "EH")
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pub name: [u8; 2],
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/// Actual value read
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pub actual: u8,
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/// Expected value (after masking)
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pub expected: u8,
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/// Whether it matches
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pub ok: bool,
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}
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/// Full config check result
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pub struct ConfigResult {
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pub checks: [RegCheck; 3],
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/// True if all checks passed
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pub all_ok: bool,
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}
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impl<I2C, E> Ntag5Link<I2C>
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where
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I2C: I2c<Error = E>,
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{
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pub fn new(i2c: I2C, addr: u8) -> Self {
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Self { i2c, addr }
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}
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/// Consume the driver and return the I2C bus.
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pub fn release(self) -> I2C {
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self.i2c
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}
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// ---- Low-level I2C commands ----
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/// Read N bytes from a 16-bit block address (READ MEMORY command).
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/// Used for EEPROM and config memory.
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pub fn read_memory(&mut self, block: u16, buf: &mut [u8]) -> Result<(), E> {
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let addr_bytes = block.to_be_bytes();
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self.i2c.write_read(self.addr, &addr_bytes, buf)
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}
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/// Write 4 bytes to a 16-bit block address (WRITE MEMORY command).
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/// Used for EEPROM writes. Each EEPROM block is 4 bytes.
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pub fn write_memory_block(&mut self, block: u16, data: &[u8; 4]) -> Result<(), E> {
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let addr_bytes = block.to_be_bytes();
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let mut buf = [0u8; 6];
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buf[0] = addr_bytes[0];
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buf[1] = addr_bytes[1];
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buf[2] = data[0];
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buf[3] = data[1];
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buf[4] = data[2];
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buf[5] = data[3];
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self.i2c.write(self.addr, &buf)
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}
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/// Write 4 bytes then read back and verify. Returns Error::VerifyFailed
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/// if the read-back doesn't match.
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pub fn write_verify_block(
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&mut self,
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block: u16,
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data: &[u8; 4],
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delay: &mut impl embedded_hal::delay::DelayNs,
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) -> Result<(), Error<E>> {
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self.write_memory_block(block, data)?;
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delay.delay_ms(5); // EEPROM write cycle ~5ms
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let mut readback = [0u8; 4];
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self.read_memory(block, &mut readback)?;
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if readback != *data {
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return Err(Error::VerifyFailed);
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}
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Ok(())
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}
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/// Read a single session register byte (READ REGISTER command).
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/// Protocol: write [BL_AD1, BL_AD0, REGA], then read 1 byte.
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pub fn read_register(&mut self, block: u16, reg_addr: u8) -> Result<u8, E> {
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let addr_bytes = block.to_be_bytes();
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let mut buf = [0u8; 1];
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self.i2c.write_read(
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self.addr,
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&[addr_bytes[0], addr_bytes[1], reg_addr],
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&mut buf,
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)?;
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Ok(buf[0])
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}
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/// Write a single session register byte (WRITE REGISTER command).
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/// Protocol: write [BL_AD1, BL_AD0, REGA, MASK, REGDATA].
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/// The MASK selects which bits to modify (1 = modify, 0 = keep).
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pub fn write_register(&mut self, block: u16, reg_addr: u8, mask: u8, data: u8) -> Result<(), E> {
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let addr_bytes = block.to_be_bytes();
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self.i2c.write(
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self.addr,
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&[addr_bytes[0], addr_bytes[1], reg_addr, mask, data],
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)
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}
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// ---- SRAM access ----
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/// Read N bytes from SRAM starting at byte offset 0.
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/// SRAM is at I2C blocks 0x10F8-0x10FF (64 blocks × 4 bytes = 256 bytes).
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/// Always reads from the start of SRAM (block-aligned).
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pub fn read_sram(&mut self, buf: &mut [u8]) -> Result<(), E> {
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self.read_memory(SRAM_BASE_BLOCK, buf)
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}
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/// Write data to SRAM starting at block offset from SRAM base.
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/// Data length must be a multiple of 4 (NTAG5 block size).
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pub fn write_sram_blocks(&mut self, block_offset: u16, data: &[u8]) -> Result<(), E> {
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for (i, chunk) in data.chunks(4).enumerate() {
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let mut block_data = [0u8; 4];
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for (j, &b) in chunk.iter().enumerate() {
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block_data[j] = b;
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}
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self.write_memory_block(SRAM_BASE_BLOCK + block_offset + i as u16, &block_data)?;
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}
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Ok(())
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}
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/// Configure FD pin for SRAM-write-by-RF indication.
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/// FD goes low when phone writes to SRAM, returns high when MCU reads SRAM.
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pub fn configure_fd_sram_write(&mut self) -> Result<(), E> {
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// ED_FD_PIN_CFG register index 1 within the session block
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// Bits 2:0 control FD output mode
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self.write_register(SESSION_ED_FD_PIN_CFG, 0x01, 0x07, FD_MODE_SRAM_RF_WRITE)
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}
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// ---- Config check ----
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/// Read session registers and compare against expected xblink config.
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/// Session registers are always readable from I2C, even if config
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/// memory is password/AES protected.
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pub fn check_config(&mut self) -> Result<ConfigResult, E> {
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// Read CONFIG_REG session register: bytes 0,1,2 = CONFIG_0, CONFIG_1, CONFIG_2
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let c0 = self.read_register(SESSION_CONFIG_REG, 0)?;
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let c1 = self.read_register(SESSION_CONFIG_REG, 1)?;
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// Read EH_CONFIG_REG session register: byte 0 = EH_CONFIG
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let eh = self.read_register(SESSION_EH_CONFIG_REG, 0)?;
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let c0_ok = (c0 & CONFIG_0_MASK) == (EXPECTED_CONFIG_0 & CONFIG_0_MASK);
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let c1_ok = (c1 & CONFIG_1_MASK) == (EXPECTED_CONFIG_1 & CONFIG_1_MASK);
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let eh_ok = (eh & EH_CONFIG_MASK) == (EXPECTED_EH_CONFIG & EH_CONFIG_MASK);
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let all_ok = c0_ok && c1_ok && eh_ok;
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Ok(ConfigResult {
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checks: [
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RegCheck { name: *b"C0", actual: c0, expected: EXPECTED_CONFIG_0, ok: c0_ok },
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RegCheck { name: *b"C1", actual: c1, expected: EXPECTED_CONFIG_1, ok: c1_ok },
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RegCheck { name: *b"EH", actual: eh, expected: EXPECTED_EH_CONFIG, ok: eh_ok },
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],
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all_ok,
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})
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}
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// ---- NDEF Type 5 text record ----
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/// Write an NDEF Type 5 text record to EEPROM user memory.
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///
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/// Layout (NFC Forum Type 5 Tag):
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/// - Block 0: CC (Capability Container) — 4 bytes
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/// - Block 1+: TLV wrapper + NDEF message
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///
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/// The text record uses "en" language code, UTF-8 encoding.
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pub fn write_ndef_text(&mut self, text: &[u8], delay: &mut impl embedded_hal::delay::DelayNs) -> Result<(), Error<E>> {
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// CC (block 0) is already present from factory/provisioning — don't overwrite.
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// NDEF message TLV:
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// [0] 03 = NDEF message TLV type
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// [1] len = total NDEF message length
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// NDEF record header:
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// [2] D1 = MB=1, ME=1, CF=0, SR=1, IL=0, TNF=01 (well-known)
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// [3] 01 = type length (1 byte: "T")
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// [4] payload_len = 3 + text.len() (status byte + "en" + text)
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// [5] 54 = type: "T" (text record)
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// NDEF payload:
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// [6] 02 = status byte: UTF-8 (bit 7=0), language code length=2
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// [7] 65 = 'e'
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// [8] 6E = 'n'
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// [9..] = text bytes
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// After message:
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// FE = terminator TLV
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let payload_len = 3 + text.len(); // status + "en" + text
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let ndef_len = 4 + payload_len; // header(3) + type(1) + payload
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let tlv_len = 2 + ndef_len; // TLV type + TLV len + NDEF message
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let total_bytes = tlv_len + 1; // + terminator TLV (FE)
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// Build the message into a buffer (max ~80 bytes for our use)
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let mut msg = [0u8; 80];
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if total_bytes > msg.len() {
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// Text too long, truncate silently — shouldn't happen for our short messages
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return Ok(());
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}
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let mut i = 0;
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msg[i] = 0x03; i += 1; // NDEF TLV type
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msg[i] = ndef_len as u8; i += 1; // NDEF TLV length
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msg[i] = 0xD1; i += 1; // NDEF record header: MB|ME|SR, TNF=well-known
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msg[i] = 0x01; i += 1; // Type length = 1
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msg[i] = payload_len as u8; i += 1; // Payload length
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msg[i] = b'T'; i += 1; // Type = "T" (text)
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msg[i] = 0x02; i += 1; // Status: UTF-8, lang len = 2
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msg[i] = b'e'; i += 1;
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msg[i] = b'n'; i += 1;
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for &b in text {
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msg[i] = b;
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i += 1;
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}
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msg[i] = 0xFE; i += 1; // Terminator TLV
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// Write to EEPROM in 4-byte blocks starting at block 1
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let mut block = 1u16;
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let mut offset = 0;
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while offset < i {
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let mut data = [0u8; 4];
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for j in 0..4 {
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if offset + j < i {
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data[j] = msg[offset + j];
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}
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}
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self.write_verify_block(block, &data, delay)?;
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block += 1;
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offset += 4;
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}
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Ok(())
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}
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/// Format the config check result as a human-readable NDEF text record.
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/// Returns the number of bytes written to `buf`.
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pub fn format_config_result(result: &ConfigResult, buf: &mut [u8]) -> usize {
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let mut i = 0;
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// Helper: append a byte slice
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fn append(buf: &mut [u8], i: &mut usize, data: &[u8]) {
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for &b in data {
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if *i < buf.len() {
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buf[*i] = b;
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*i += 1;
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}
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}
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}
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// Helper: append hex byte as 2 ASCII chars
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fn hex(buf: &mut [u8], i: &mut usize, val: u8) {
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const HEX: &[u8; 16] = b"0123456789ABCDEF";
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if *i + 1 < buf.len() {
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buf[*i] = HEX[(val >> 4) as usize];
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*i += 1;
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buf[*i] = HEX[(val & 0x0F) as usize];
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*i += 1;
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}
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}
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append(buf, &mut i, b"xblink cfg:");
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if result.all_ok {
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append(buf, &mut i, b" OK ");
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} else {
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append(buf, &mut i, b" BAD ");
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}
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for check in &result.checks {
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append(buf, &mut i, &check.name);
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append(buf, &mut i, b":");
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hex(buf, &mut i, check.actual);
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if check.ok {
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append(buf, &mut i, b"ok ");
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} else {
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append(buf, &mut i, b"!=");
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hex(buf, &mut i, check.expected);
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append(buf, &mut i, b" ");
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}
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}
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i
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}
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/// Run config check and write result as NDEF text record.
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/// Returns Ok(true) if config matches, Ok(false) if mismatch,
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/// Err(VerifyFailed) if EEPROM write-verify failed,
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/// Err(I2c(e)) if I2C communication failed.
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pub fn check_and_write_ndef(&mut self, delay: &mut impl embedded_hal::delay::DelayNs) -> Result<bool, Error<E>> {
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let result = self.check_config()?;
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let all_ok = result.all_ok;
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let mut buf = [0u8; 64];
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let len = Self::format_config_result(&result, &mut buf);
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self.write_ndef_text(&buf[..len], delay)?;
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Ok(all_ok)
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}
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}
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