Add pattern library, NTAG5 config check, NDEF writer (M3+M4)

M3: 5 autonomous LP5562 engine patterns (breathe, heartbeat, slow_pulse,
rgb_cycle, color_wash) with dual LED mode support (RGBW/Mono3) and
2mA/ch current for EH-realistic power budget.

M4: NTAG5Link I2C slave driver with session register reads, EEPROM
write-verify, and NDEF Type 5 text record output. Config check validates
CONFIG_0, CONFIG_1, EH_CONFIG against expected values and writes result
as NFC-readable text. Verified on hardware: config check passes, NDEF
readable via ISO15693 from phone.

Key findings from hardware testing:
- SRAM passthrough arbiter blocks NFC reads while I2C bus is active
  (resolves naturally when MCU enters STANDBY — noted in M7 plan)
- NTAG5 must be in I2C slave mode (not master) for MCU communication
- EH config mask set to 0x00 (skip check during external power testing)

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

docs/STATUS.md

@@ -1,6 +1,6 @@
 # xblink Project Status
 
-**Current Milestone**: M3 — Hardcoded Pattern Library
+**Current Milestone**: M5 — Boot-from-EEPROM
 **Last Updated**: 2026-03-05
 
 ---
@@ -34,24 +34,26 @@
 - [x] Verify LP5562 runs patterns autonomously (MCU idle loop)
 - [x] Verify MCU can stop and switch patterns (8s cycle between all 3)
 
-### M3: Hardcoded Pattern Library
+### M3: Hardcoded Pattern Library (COMPLETE)
 
-- [ ] Define 4-5 const patterns in firmware
-- [ ] Implement pattern selector (compile-time or boot-cycle)
-- [ ] Reduce LED current to 2-5mA/ch (EH-realistic budget)
-- [ ] Document actual engine program structures (informs M5 format design)
+- [x] Define 5 const patterns in firmware (breathe, heartbeat, slow_pulse, rgb_cycle, color_wash)
+- [x] Implement pattern selector (cycle through patterns, 15s each)
+- [x] Reduce LED current to 2mA/ch (EH-realistic budget)
+- [x] Document engine program structures (`docs/lp5562-engine-reference.md`)
 
 ## Group B — Add NTAG5Link
 
 **Hardware needed**: + NTAG5Link Click board + I2C jumper
 
-### M4: NTAG5 EEPROM Read/Write
+### M4: NTAG5 EEPROM Read/Write (COMPLETE)
 
-- [ ] Write `Ntag5Link<I2C>` driver (`src/ntag5/mod.rs`)
-- [ ] Implement register map (`src/ntag5/registers.rs`)
-- [ ] Implement EEPROM block read/write
-- [ ] Implement session register access
-- [ ] Test round-trip: PCSC writes EEPROM, MCU reads back, displays on LEDs
+- [x] Write `Ntag5Link<I2C>` driver (`src/ntag5/mod.rs`)
+- [x] Implement session register access (CONFIG_0, CONFIG_1, EH_CONFIG)
+- [x] Implement EEPROM block read/write with write-verify
+- [x] Config check: read session regs, compare against expected, write NDEF result
+- [x] NDEF Type 5 text record writer for config check output
+- [x] Verified on hardware: config check passes, NDEF readable via NFC
+- [ ] Register map module (`src/ntag5/registers.rs`) — deferred, constants in mod.rs for now
 
 ### M5: Boot-from-EEPROM