Add hall sensor circuit design, NTAG5 config check tool, I2C bus docs
- Hall sensor + LP5562 EN wired-AND circuit design (DRV5032FB/FE, 1M pull-up, open-drain topology) with three interaction modes: boot-time recovery, tap-to-swap, hold-to-confirm recovery - NTAG5 config check tool (tools/ntag5_config_check.py) using uFCoder library for ISO15693 transparent mode via uFR Zero reader. Supports inventory + addressed mode for multi-tag fields. - Updated DEVELOPMENT_PLAN with I2C bus management notes for LP5562 (0x30) + NTAG5Link (0x54) shared bus - Updated README with wired-AND hardware diagram, hall sensor interaction section, and updated wiring table - Updated CLAUDE.md with LP5562 EN wired-AND topology docs - Updated STATUS.md with hall sensor decisions and hardware inventory Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
michael
@@ -80,6 +80,12 @@ This gives us real pattern data to inform the EEPROM storage format later (M5),
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**Important**: The MCU accesses NTAG5Link as a standard I2C slave at address 0x54 — plain register read/write. This is NOT the NFC-side ISO15693 custom commands used by the Python ntag5sensor tooling.
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**I2C bus management**: LP5562 (0x30) and NTAG5Link (0x54) share the same I2C bus (A4/A5). Both addresses are used simultaneously — the MCU talks to each device by its address. Key considerations:
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- Both are I2C slave devices with non-conflicting addresses
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- LP5562 engines run autonomously after programming — no ongoing I2C traffic needed
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- Pause LP5562 engines (set exec to Hold) before lengthy NTAG5 I2C transactions to avoid any bus contention edge cases
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- NTAG5Link's use_case must be set to `i2c_slave` (not `i2c_master`) so it doesn't drive the bus
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**Tasks**:
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1. Write `src/ntag5/mod.rs` — `Ntag5Link<I2C>` struct, generic over `embedded_hal::i2c::I2c`
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2. Write `src/ntag5/registers.rs` — register map constants from `ntag5link.py`
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@@ -182,24 +188,37 @@ Typical 3-engine pattern: 16 + 3×34 + 4 = **122 bytes** (fits easily in 2048B E
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| LP5562 quiescent | ~0.5mA | ~0.5mA |
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| LP5562 LEDs (4ch @ 3mA) | ~12mA | ~12mA |
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| NTAG5Link | ~100µA | ~1µA |
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| Hall sensor (DRV5032) | ~1.6µA | ~1.6µA |
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| EN pull-up (1M @ 3V) | ~0 | ~0 (3µA only when EN low) |
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| **Total** | **~17mA** | **~12.5mA** |
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Key insight: LED current dominates. MCU sleep saves ~4mA. Total must stay under EH max (~12.5mA), so LED current must be limited.
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**Done when**: MCU sleeps after boot, LP5562 runs patterns, MCU wakes on NFC to accept new pattern.
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### M8: Recovery Mode
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### M8: Recovery Mode + Pattern Swap
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**Goal**: Hall sensor provides safe mode entry for post-implant recovery.
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**Goal**: Hall sensor provides pattern cycling (tap) and safe mode entry (hold + confirm).
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**Circuit**: Wired-AND on LP5562 EN — hall sensor (open-drain) + MCU GPIO (open-drain) + pull-up resistor. Magnet presence forces EN low at hardware level, independent of MCU state. Hall output also connected to MCU EIC pin for interrupt/wake. See `docs/plans/2026-03-03-hall-en-design.md`.
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**Interaction model**:
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- **Boot-time recovery**: Hall asserted at power-on → EN held low (hardware), MCU skips EEPROM, loads default pattern, stays awake
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- **Tap (<1s)**: LEDs off instantly (hardware EN drop) → magnet removed → MCU loads next pattern → LEDs back
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- **Hold (>3s + confirm)**: LEDs off (hardware) → magnet removed → MCU blinks warning (3x red) → 2s window for confirmation tap → if confirmed, enters recovery mode. No second tap → resumes normal operation
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- **MCU crashed + magnet**: Hall still kills EN (hardware safety)
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**Tasks**:
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1. Wire hall sensor to EIC-capable GPIO pin
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2. Boot-time check: if hall sensor asserted → recovery mode
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3. Recovery behavior: load hardcoded solid white (low brightness), skip EEPROM, stay awake
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4. Set recovery flag in SRAM so phone app can detect it
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5. Add hall sensor as runtime EIC wake source (e.g., cycle patterns)
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1. Wire hall sensor: open-drain output to EN line (wired-AND) + separate wire to EIC pin
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2. Add pull-up resistor (100k-1M) on EN line
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3. Configure MCU GPIO (D0/A0) as open-drain for EN control
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4. Implement EIC interrupt handler for hall sensor pin
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5. Implement boot-time recovery: read hall GPIO at startup, if asserted → default pattern, skip EEPROM
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6. Implement runtime state machine: tap detection, hold timing, warning blink, recovery confirmation
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7. Recovery behavior: load hardcoded solid white (low brightness), skip EEPROM, stay awake
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8. Set recovery flag in SRAM so phone app can detect it
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**Done when**: Holding magnet near hall sensor at boot triggers recovery mode with default LED pattern.
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**Done when**: Boot-time recovery works (magnet at power-on), tap cycles patterns at runtime, hold + confirm enters runtime recovery, hardware EN kill works even if MCU is unresponsive.
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### M9: Power Characterization
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@@ -272,7 +291,7 @@ Deferred until Groups A-D are solid.
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| Risk | Severity | Mitigation |
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|------|----------|------------|
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| Power budget too tight for 4ch LED | High | Limit current to 2-3mA/ch, use pulsed patterns, run fewer channels |
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| I2C bus contention (LP5562 + NTAG5) | Medium | Pause LP5562 engines before NTAG5 I2C access, resume after |
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| I2C bus contention (LP5562 + NTAG5) | Medium | Non-conflicting addresses (0x30 vs 0x54). Pause LP5562 engines during NTAG5 I2C bursts. Verify NTAG5 is in i2c_slave mode (not i2c_master) |
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| EEPROM write endurance (~100K cycles) | Low | SRAM for transient comms, EEPROM only for pattern persistence |
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| Boot time too slow | Low | Estimated ~15-20ms — appears instant to user |
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| NFC coupling distance too short | Medium | Optimize antenna, low field strength EH mode, accept 1-3cm |
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@@ -131,6 +131,9 @@
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| Firmware update strategy | Deferred | UF2 for dev, NFC OTA evaluated later |
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| NTAG5Link I2C slave address | Assumed 0x54 | Verify in M4 with Click board |
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| Pattern binary format | Deferred to M5 | Design after M2-M3 engine experience |
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| Hall sensor + EN circuit | Designed | Wired-AND: hall + MCU open-drain on EN with 1M pull-up. See `docs/plans/2026-03-03-hall-en-design.md` |
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| Hall sensor part selection | Decided | DRV5032FB (SOT-23, 8.4mT, prototype) → DRV5032FE (X2SON 1x1mm, final PCB) |
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| EN pull-up value | Decided | 1M — zero steady-state draw, 3µA when EN low, ~10µs rise time |
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## Hardware Inventory
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@@ -140,6 +143,6 @@
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| LP5562EVM | Available | TI eval module, RGBW LEDs, I2C addr 0x30 |
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| Mini-USB cable | Not on hand | Needed to flash XIAO M0 |
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| NTAG5 Link Click | Available, partially wired | Missing I2C jumper to XIAO |
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| Hall effect sensor | Not available | Need to source |
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| Hall effect sensor | Not available | Need to source — TI DRV5032FB (SOT-23) for prototype |
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| ACR1552 PCSC reader | Available | For ntag5sensor Python tooling |
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| Multimeter | Available | For power budget measurements |
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159
docs/plans/2026-03-03-hall-en-design.md
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159
docs/plans/2026-03-03-hall-en-design.md
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@@ -0,0 +1,159 @@
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# Hall Sensor + LP5562 EN Wired-AND Circuit Design
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**Date**: 2026-03-03
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**Status**: Design in progress
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## Problem
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The implant needs a hall sensor for three functions:
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1. **Pattern swap** — quick magnet tap cycles to the next stored pattern
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2. **Runtime recovery** — long hold + confirmation tap enters safe mode
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3. **Boot-time recovery** — magnet present at power-on skips EEPROM, loads default
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4. **Hardware safety** — LEDs forced off by magnet even if MCU firmware has crashed
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These must work within extreme space and power constraints (energy-harvested implant).
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## Circuit: Wired-AND on LP5562 EN
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Zero extra active components. Hall sensor and MCU share the EN line via open-drain outputs.
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```
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VCC (3.0V from NTAG5Link EH)
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1M (pull-up resistor)
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EN ------+------- MCU D0/A0 (open-drain)
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+------- Hall sensor OUT (open-drain, active-low)
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LP5562 EN pin
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Hall sensor OUT ---- MCU EIC pin (separate connection for interrupt/wake)
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```
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### How it works
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| State | MCU pin | Hall sensor | EN line | LP5562 |
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|-------|---------|-------------|---------|--------|
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| Normal operation | High-Z | High-Z (no magnet) | High (pull-up) | On |
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| Magnet present | High-Z | Driving low | Low | Off |
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| MCU disabling LP5562 | Driving low | High-Z | Low | Off |
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| Magnet + MCU low | Driving low | Driving low | Low | Off |
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### Pull-up resistor: 1M
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- Steady-state current: ~0 (both open-drains high-Z, no path to ground)
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- Current when EN low: 3V / 1M = 3 µA (only during magnet or MCU-driven low)
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- Rise time: ~10 µs (1M x ~10pF parasitic) — instant from human perspective
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- LP5562 EN input is high-impedance CMOS — no DC loading
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## Hall Sensor: TI DRV5032
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| Variant | Use | Iq | Threshold | Output | Package |
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|---------|-----|-----|-----------|--------|---------|
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| **DRV5032FB** | Prototype | 1.6 µA | 8.4 mT (omnipolar) | Open-drain | SOT-23 |
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| **DRV5032FE** | Final PCB | 0.55 µA | 4.5 mT (omnipolar) | Open-drain | X2SON (1x1mm) |
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- **Omnipolar**: Triggers on either magnetic pole (user doesn't need to orient magnet)
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- **8.4 mT threshold (FB)**: Higher threshold = harder to accidentally trigger. Requires deliberate, close magnet interaction. Good for "don't accidentally enter recovery" requirement.
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- **Open-drain, active-low**: Required for wired-AND topology
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- **SOT-23 for prototyping**: Easy to hand-solder; X2SON for final implant PCB
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## Interaction Model
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### Pattern Swap (tap <1s)
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1. Magnet near → hall pulls EN low → LEDs off instantly (hardware, zero MCU latency)
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2. MCU wakes via EIC interrupt on hall sensor pin, starts timer
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3. Magnet removed (hall goes high-Z, pull-up restores EN)
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4. MCU detects short press (<1s) → loads next stored pattern → LEDs back on
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### Runtime Recovery (hold >3s + confirm)
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1. Magnet near → EN low (hardware), MCU wakes via EIC
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2. MCU counts hold duration while hall stays asserted
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3. Magnet removed after >3s → MCU notes "long hold detected"
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4. MCU re-enables LP5562 → blinks warning pattern (3x red flash)
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5. MCU waits 2s for confirmation tap
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6. Confirmation tap received → enters recovery mode
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7. No confirmation → resumes normal operation (reloads previous pattern)
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### Boot-time Recovery
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1. NFC field arrives, VOUT powers system
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2. Hall sensor already active (magnet was present before power) → EN held low by hardware
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3. MCU boots, reads hall GPIO → asserted → boot-time recovery
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4. Loads hardcoded default pattern (solid white, low brightness)
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5. Skips EEPROM pattern data
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6. Sets recovery flag in SRAM for phone app detection
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7. When magnet removed, EN goes high, default pattern runs
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### Hardware Safety (MCU crashed)
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- Holding magnet forces EN low at circuit level regardless of MCU state
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- No firmware dependency — pure hardware path
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- Magnet removal restores EN via pull-up (LP5562 resumes last-programmed pattern)
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## Firmware State Machine (M8)
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```
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┌─────────────┐
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power-on -->│ BOOT_CHECK │
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└──────┬──────┘
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hall low? │
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┌───yes─────┼────no───┐
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v │ v
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┌──────────┐ │ ┌─────────────┐
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│ RECOVERY │ │ │ RUNNING │<──────────────┐
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└──────────┘ │ └──────┬──────┘ │
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│ hall EIC │ │
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│ interrupt│ │
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│ v │
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│ ┌─────────────┐ │
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│ │ HALL_ACTIVE │ │
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│ └──────┬──────┘ │
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│ hall released │
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│ │ │ │
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│ <1s >3s │
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│ │ │ │
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│ v v │
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│ ┌──────┐ ┌──────────────┐ │
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│ │ SWAP │ │ WARN_BLINK │ │
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│ └──┬───┘ └──────┬───────┘ │
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│ │ hall tap │ no tap │
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│ │ in 2s? │ │
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│ │ ┌──yes ┌──no │
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│ │ v v │
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│ │ ┌────────┐ │ │
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│ │ │RECOVERY│ │ │
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│ │ └────────┘ │ │
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│ └──────────────┴──────────┘
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```
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States:
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- **BOOT_CHECK**: Read hall GPIO. If asserted → RECOVERY. Else → RUNNING.
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- **RUNNING**: LP5562 engines active, MCU in STANDBY sleep. Wakes on hall EIC.
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- **HALL_ACTIVE**: Magnet detected. Timer running. Waiting for release.
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- **SWAP**: Load next pattern, re-enable LP5562 → RUNNING.
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- **WARN_BLINK**: Blink 3x red. Wait 2s for confirmation tap.
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- **RECOVERY**: Default pattern, skip EEPROM, stay awake, set SRAM flag.
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## Power Impact
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| Component | Added draw | When |
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|-----------|-----------|------|
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| Hall sensor (DRV5032FB) | 1.6 µA | Always (quiescent) |
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| Pull-up resistor (1M) | 3 µA | Only when EN is low (magnet or MCU-driven) |
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| Pull-up resistor (1M) | ~0 | Steady state (EN high, no current path) |
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Total added quiescent: **~1.6 µA** — negligible vs LP5562 LED current (~12 mA).
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## Open Questions
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| Question | Notes |
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|----------|-------|
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| Debounce needed? | Hall sensors are usually clean (no mechanical bounce), but verify with DRV5032 |
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| EIC pin selection on SAMD21E | Must be EIC-capable for wake from STANDBY. Check SAMD21E pinout. |
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| Magnet strength/distance | What N52 neodymium size triggers DRV5032FB at implant depth (~3-5mm subdermal)? |
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| Multiple stored patterns | How many patterns to cycle through? Currently TBD (depends on EEPROM format, M5) |
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90
docs/plans/2026-03-03-ntag5-config-check.md
Normal file
90
docs/plans/2026-03-03-ntag5-config-check.md
Normal file
@@ -0,0 +1,90 @@
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# NTAG5Link Config Verification via uFR Zero
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**Date**: 2026-03-03
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**Status**: Tool written, reader connection blocked
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## Goal
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Read-only verification that the NTAG5Link Click board's configuration matches xblink requirements, using the Digital Logic uFR Zero Multi-ISO reader.
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## Tool
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`tools/ntag5_config_check.py` — Python script using uFCoder library (ctypes) in ISO15693 transparent mode.
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Features:
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- ISO15693 INVENTORY to discover all tags by UID
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- Addressed mode for all config reads (supports multiple tags in field)
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- Reads CONFIG block (0x37) and EH/ED CONFIG block (0x3D)
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- NXP system info for interface type verification
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- Checks against xblink expected config values
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## Expected Config
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| Setting | Expected | Config Location |
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|---------|----------|----------------|
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| EH mode | low_field_strength | CONFIG byte 0, bits 3:2 = 10 |
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| Use case | i2c_slave | CONFIG byte 1, bits 5:4 = 00 |
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| SRAM enabled | true | CONFIG byte 1, bit 1 = 1 |
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| Arbiter mode | sram_passthrough | CONFIG byte 1, bits 3:2 = 10 |
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| EH enable | true | EH_CONFIG byte 0, bit 0 = 1 |
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| EH voltage | 3.0V | EH_CONFIG byte 0, bits 2:1 = 10 |
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## Reader Connection Issue
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**Problem**: uFCoder library returns `UFR_TIMEOUT_ERR` (0x1002) for all `ReaderOpenEx` parameter combinations.
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**USB device**: `10c4:ea60` — Silicon Labs CP2102 USB to UART Bridge Controller, iSerial "0001". Generic descriptor, no D-Logic branding in USB strings.
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**Raw serial investigation**:
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- At 1 Mbps (expected uFR baud): responds with `00 80` (2 bytes) — not a valid uFR protocol frame (expected 6+ bytes with `0x55...0xAA` framing)
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- At 115200 bps: returns ASCII shell commands mentioning "systemctl", "proxmark3" paths
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- At 250 Kbps: returns structured but unrecognized data
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**Possible causes**:
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1. Device may not be a uFR Zero — the CP210x bridge has generic descriptors
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2. Reader firmware may need updating
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3. Reader may be in a non-standard mode
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4. Different hardware variant requiring different protocol
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**Next steps**:
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1. Physically verify the device is indeed the uFR Zero (check labels, LEDs)
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2. Try the D-Logic `ufr_online` Windows utility to confirm reader identity
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3. If confirmed as uFR Zero, check firmware version and update if needed
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4. Alternative: use the ACR1552 PCSC reader with ntag5sensor directly (requires porting the reader to share the field with NTAG5 Click)
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## Fallback Plan: ntag5sensor + ACR1552
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If the uFR Zero connection cannot be resolved, use the existing ntag5sensor Python tooling with the ACR1552 PCSC reader:
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```python
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# From ntag5sensor — already has full config read/write support
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chip = NTAG5Link(reader)
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config = chip.get_config_info()
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eh_config = chip.get_eh_ed_config_info()
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```
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The ACR1552 is already proven with ntag5sensor. Only change needed: physically position the ACR1552 over the NTAG5 Click board instead of the uFR Zero.
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## Config Change Plan (if mismatches found)
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Use ntag5sensor's write functions (via ACR1552 or adapted for uFR Zero):
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```python
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# Set I2C slave mode + SRAM passthrough + SRAM enable
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chip.write_config1(
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sram_enable=True,
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arbiter_mode=NXP_CONFIG_1_ARBITER_MODE_SRAM_PASSTHROUGH,
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use_case=NXP_CONFIG_1_USE_CASE_CONF_I2C_SLAVE
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)
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# Set EH: 3.0V, enabled, current limit TBD
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chip.write_eh_ed_config(
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enable=True,
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voltage=NXP_EH_CONFIG_EH_VOUT_V_SEL_3_0,
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current=NXP_EH_CONFIG_EH_VOUT_I_SEL_12_5, # max for testing
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ed_config=NXP_ED_CONFIG_NFC_FIELD_DETECT
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)
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# Set EH mode in CONFIG byte 0
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chip.write_config0(eh_mode=NXP_CONFIG_0_EH_MODE_LOW_FIELD_STRENGTH)
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```
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