- Hall sensor + LP5562 EN wired-AND circuit design (DRV5032FB/FE, 1M pull-up, open-drain topology) with three interaction modes: boot-time recovery, tap-to-swap, hold-to-confirm recovery - NTAG5 config check tool (tools/ntag5_config_check.py) using uFCoder library for ISO15693 transparent mode via uFR Zero reader. Supports inventory + addressed mode for multi-tag fields. - Updated DEVELOPMENT_PLAN with I2C bus management notes for LP5562 (0x30) + NTAG5Link (0x54) shared bus - Updated README with wired-AND hardware diagram, hall sensor interaction section, and updated wiring table - Updated CLAUDE.md with LP5562 EN wired-AND topology docs - Updated STATUS.md with hall sensor decisions and hardware inventory Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
3.5 KiB
NTAG5Link Config Verification via uFR Zero
Date: 2026-03-03 Status: Tool written, reader connection blocked
Goal
Read-only verification that the NTAG5Link Click board's configuration matches xblink requirements, using the Digital Logic uFR Zero Multi-ISO reader.
Tool
tools/ntag5_config_check.py — Python script using uFCoder library (ctypes) in ISO15693 transparent mode.
Features:
- ISO15693 INVENTORY to discover all tags by UID
- Addressed mode for all config reads (supports multiple tags in field)
- Reads CONFIG block (0x37) and EH/ED CONFIG block (0x3D)
- NXP system info for interface type verification
- Checks against xblink expected config values
Expected Config
| Setting | Expected | Config Location |
|---|---|---|
| EH mode | low_field_strength | CONFIG byte 0, bits 3:2 = 10 |
| Use case | i2c_slave | CONFIG byte 1, bits 5:4 = 00 |
| SRAM enabled | true | CONFIG byte 1, bit 1 = 1 |
| Arbiter mode | sram_passthrough | CONFIG byte 1, bits 3:2 = 10 |
| EH enable | true | EH_CONFIG byte 0, bit 0 = 1 |
| EH voltage | 3.0V | EH_CONFIG byte 0, bits 2:1 = 10 |
Reader Connection Issue
Problem: uFCoder library returns UFR_TIMEOUT_ERR (0x1002) for all ReaderOpenEx parameter combinations.
USB device: 10c4:ea60 — Silicon Labs CP2102 USB to UART Bridge Controller, iSerial "0001". Generic descriptor, no D-Logic branding in USB strings.
Raw serial investigation:
- At 1 Mbps (expected uFR baud): responds with
00 80(2 bytes) — not a valid uFR protocol frame (expected 6+ bytes with0x55...0xAAframing) - At 115200 bps: returns ASCII shell commands mentioning "systemctl", "proxmark3" paths
- At 250 Kbps: returns structured but unrecognized data
Possible causes:
- Device may not be a uFR Zero — the CP210x bridge has generic descriptors
- Reader firmware may need updating
- Reader may be in a non-standard mode
- Different hardware variant requiring different protocol
Next steps:
- Physically verify the device is indeed the uFR Zero (check labels, LEDs)
- Try the D-Logic
ufr_onlineWindows utility to confirm reader identity - If confirmed as uFR Zero, check firmware version and update if needed
- Alternative: use the ACR1552 PCSC reader with ntag5sensor directly (requires porting the reader to share the field with NTAG5 Click)
Fallback Plan: ntag5sensor + ACR1552
If the uFR Zero connection cannot be resolved, use the existing ntag5sensor Python tooling with the ACR1552 PCSC reader:
# From ntag5sensor — already has full config read/write support
chip = NTAG5Link(reader)
config = chip.get_config_info()
eh_config = chip.get_eh_ed_config_info()
The ACR1552 is already proven with ntag5sensor. Only change needed: physically position the ACR1552 over the NTAG5 Click board instead of the uFR Zero.
Config Change Plan (if mismatches found)
Use ntag5sensor's write functions (via ACR1552 or adapted for uFR Zero):
# Set I2C slave mode + SRAM passthrough + SRAM enable
chip.write_config1(
sram_enable=True,
arbiter_mode=NXP_CONFIG_1_ARBITER_MODE_SRAM_PASSTHROUGH,
use_case=NXP_CONFIG_1_USE_CASE_CONF_I2C_SLAVE
)
# Set EH: 3.0V, enabled, current limit TBD
chip.write_eh_ed_config(
enable=True,
voltage=NXP_EH_CONFIG_EH_VOUT_V_SEL_3_0,
current=NXP_EH_CONFIG_EH_VOUT_I_SEL_12_5, # max for testing
ed_config=NXP_ED_CONFIG_NFC_FIELD_DETECT
)
# Set EH mode in CONFIG byte 0
chip.write_config0(eh_mode=NXP_CONFIG_0_EH_MODE_LOW_FIELD_STRENGTH)