- Hall sensor + LP5562 EN wired-AND circuit design (DRV5032FB/FE, 1M pull-up, open-drain topology) with three interaction modes: boot-time recovery, tap-to-swap, hold-to-confirm recovery - NTAG5 config check tool (tools/ntag5_config_check.py) using uFCoder library for ISO15693 transparent mode via uFR Zero reader. Supports inventory + addressed mode for multi-tag fields. - Updated DEVELOPMENT_PLAN with I2C bus management notes for LP5562 (0x30) + NTAG5Link (0x54) shared bus - Updated README with wired-AND hardware diagram, hall sensor interaction section, and updated wiring table - Updated CLAUDE.md with LP5562 EN wired-AND topology docs - Updated STATUS.md with hall sensor decisions and hardware inventory Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
7.5 KiB
7.5 KiB
Hall Sensor + LP5562 EN Wired-AND Circuit Design
Date: 2026-03-03 Status: Design in progress
Problem
The implant needs a hall sensor for three functions:
- Pattern swap — quick magnet tap cycles to the next stored pattern
- Runtime recovery — long hold + confirmation tap enters safe mode
- Boot-time recovery — magnet present at power-on skips EEPROM, loads default
- Hardware safety — LEDs forced off by magnet even if MCU firmware has crashed
These must work within extreme space and power constraints (energy-harvested implant).
Circuit: Wired-AND on LP5562 EN
Zero extra active components. Hall sensor and MCU share the EN line via open-drain outputs.
VCC (3.0V from NTAG5Link EH)
|
1M (pull-up resistor)
|
EN ------+------- MCU D0/A0 (open-drain)
|
+------- Hall sensor OUT (open-drain, active-low)
|
LP5562 EN pin
Hall sensor OUT ---- MCU EIC pin (separate connection for interrupt/wake)
How it works
| State | MCU pin | Hall sensor | EN line | LP5562 |
|---|---|---|---|---|
| Normal operation | High-Z | High-Z (no magnet) | High (pull-up) | On |
| Magnet present | High-Z | Driving low | Low | Off |
| MCU disabling LP5562 | Driving low | High-Z | Low | Off |
| Magnet + MCU low | Driving low | Driving low | Low | Off |
Pull-up resistor: 1M
- Steady-state current: ~0 (both open-drains high-Z, no path to ground)
- Current when EN low: 3V / 1M = 3 µA (only during magnet or MCU-driven low)
- Rise time: ~10 µs (1M x ~10pF parasitic) — instant from human perspective
- LP5562 EN input is high-impedance CMOS — no DC loading
Hall Sensor: TI DRV5032
| Variant | Use | Iq | Threshold | Output | Package |
|---|---|---|---|---|---|
| DRV5032FB | Prototype | 1.6 µA | 8.4 mT (omnipolar) | Open-drain | SOT-23 |
| DRV5032FE | Final PCB | 0.55 µA | 4.5 mT (omnipolar) | Open-drain | X2SON (1x1mm) |
- Omnipolar: Triggers on either magnetic pole (user doesn't need to orient magnet)
- 8.4 mT threshold (FB): Higher threshold = harder to accidentally trigger. Requires deliberate, close magnet interaction. Good for "don't accidentally enter recovery" requirement.
- Open-drain, active-low: Required for wired-AND topology
- SOT-23 for prototyping: Easy to hand-solder; X2SON for final implant PCB
Interaction Model
Pattern Swap (tap <1s)
- Magnet near → hall pulls EN low → LEDs off instantly (hardware, zero MCU latency)
- MCU wakes via EIC interrupt on hall sensor pin, starts timer
- Magnet removed (hall goes high-Z, pull-up restores EN)
- MCU detects short press (<1s) → loads next stored pattern → LEDs back on
Runtime Recovery (hold >3s + confirm)
- Magnet near → EN low (hardware), MCU wakes via EIC
- MCU counts hold duration while hall stays asserted
- Magnet removed after >3s → MCU notes "long hold detected"
- MCU re-enables LP5562 → blinks warning pattern (3x red flash)
- MCU waits 2s for confirmation tap
- Confirmation tap received → enters recovery mode
- No confirmation → resumes normal operation (reloads previous pattern)
Boot-time Recovery
- NFC field arrives, VOUT powers system
- Hall sensor already active (magnet was present before power) → EN held low by hardware
- MCU boots, reads hall GPIO → asserted → boot-time recovery
- Loads hardcoded default pattern (solid white, low brightness)
- Skips EEPROM pattern data
- Sets recovery flag in SRAM for phone app detection
- When magnet removed, EN goes high, default pattern runs
Hardware Safety (MCU crashed)
- Holding magnet forces EN low at circuit level regardless of MCU state
- No firmware dependency — pure hardware path
- Magnet removal restores EN via pull-up (LP5562 resumes last-programmed pattern)
Firmware State Machine (M8)
┌─────────────┐
power-on -->│ BOOT_CHECK │
└──────┬──────┘
hall low? │
┌───yes─────┼────no───┐
v │ v
┌──────────┐ │ ┌─────────────┐
│ RECOVERY │ │ │ RUNNING │<──────────────┐
└──────────┘ │ └──────┬──────┘ │
│ hall EIC │ │
│ interrupt│ │
│ v │
│ ┌─────────────┐ │
│ │ HALL_ACTIVE │ │
│ └──────┬──────┘ │
│ hall released │
│ │ │ │
│ <1s >3s │
│ │ │ │
│ v v │
│ ┌──────┐ ┌──────────────┐ │
│ │ SWAP │ │ WARN_BLINK │ │
│ └──┬───┘ └──────┬───────┘ │
│ │ hall tap │ no tap │
│ │ in 2s? │ │
│ │ ┌──yes ┌──no │
│ │ v v │
│ │ ┌────────┐ │ │
│ │ │RECOVERY│ │ │
│ │ └────────┘ │ │
│ └──────────────┴──────────┘
States:
- BOOT_CHECK: Read hall GPIO. If asserted → RECOVERY. Else → RUNNING.
- RUNNING: LP5562 engines active, MCU in STANDBY sleep. Wakes on hall EIC.
- HALL_ACTIVE: Magnet detected. Timer running. Waiting for release.
- SWAP: Load next pattern, re-enable LP5562 → RUNNING.
- WARN_BLINK: Blink 3x red. Wait 2s for confirmation tap.
- RECOVERY: Default pattern, skip EEPROM, stay awake, set SRAM flag.
Power Impact
| Component | Added draw | When |
|---|---|---|
| Hall sensor (DRV5032FB) | 1.6 µA | Always (quiescent) |
| Pull-up resistor (1M) | 3 µA | Only when EN is low (magnet or MCU-driven) |
| Pull-up resistor (1M) | ~0 | Steady state (EN high, no current path) |
Total added quiescent: ~1.6 µA — negligible vs LP5562 LED current (~12 mA).
Open Questions
| Question | Notes |
|---|---|
| Debounce needed? | Hall sensors are usually clean (no mechanical bounce), but verify with DRV5032 |
| EIC pin selection on SAMD21E | Must be EIC-capable for wake from STANDBY. Check SAMD21E pinout. |
| Magnet strength/distance | What N52 neodymium size triggers DRV5032FB at implant depth (~3-5mm subdermal)? |
| Multiple stored patterns | How many patterns to cycle through? Currently TBD (depends on EEPROM format, M5) |