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xblink/docs/STATUS.md
michael bae64c1e3a Initial project scaffold for xblink NFC-powered LED implant 
Set up Rust embedded project targeting SAMD21 (thumbv6m-none-eabi) with
XIAO M0 BSP for dev board prototyping. Includes LP5562 EN pin control
on D0/A0, project documentation (README, CLAUDE.md), phased status
tracker, and detailed development plan covering LP5562 driver integration,
NTAG5Link I2C driver, pattern storage format, power management, NFC
communication protocol, recovery mode, and firmware update strategy.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-03-03 09:32:30 -08:00

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xblink Project Status

Current Phase: Phase 0 — Project Setup Last Updated: 2026-03-03

Phase 0 — Project Setup

  • Initialize git repository
  • Initialize Rust project with cargo init
  • Configure .cargo/config.toml for thumbv6m-none-eabi
  • Set up Cargo.toml with XIAO M0 BSP and embedded-hal 1.0
  • Create .gitignore
  • Create initial src/main.rs (blink + LP5562 EN pin on D0/A0)
  • Create project directory structure (src/led/, src/ntag5/, src/pattern/, docs/)
  • Create README.md
  • Create CLAUDE.md
  • Create docs/STATUS.md (this file)
  • Create docs/DEVELOPMENT_PLAN.md
  • Verify cargo build --release compiles
  • Initial git commit

Phase 1 — LP5562 Driver Integration

  • Copy LP5562 driver from ../ntag5-samd21-lp562/src/lp5562.rs
  • Define LedController trait in src/led/mod.rs
  • Wrap LP5562 driver to implement LedController
  • Add GPIO EN pin control to LP5562 wrapper (D0/A0 hardware enable)
  • Test LP5562 direct PWM on XIAO M0 + LP5562EVM
  • Test LP5562 engine programs (breathing, color cycling)
  • Implement SimplePwm driver as second LedController implementation

Phase 2 — NTAG5Link Driver (MCU-side I2C Slave)

  • Implement NTAG5Link register map (src/ntag5/registers.rs)
  • Implement EEPROM block read/write via I2C (src/ntag5/eeprom.rs)
  • Implement SRAM mailbox read/write (src/ntag5/sram.rs)
  • Implement session register access
  • Test EEPROM read/write with XIAO M0 + NTAG5Link Click board
  • Test SRAM mailbox read/write
  • Verify round-trip: write pattern via PCSC reader, read back on MCU

Phase 3 — Pattern Storage Format

  • Design binary pattern format (header + engine programs + LED mapping)
  • Document format in docs/PATTERN_FORMAT.md
  • Implement pattern deserializer (src/pattern/mod.rs)
  • Implement LP5562 engine program builder from pattern data (src/pattern/engine.rs)
  • Implement pattern serializer (for MCU-side EEPROM writes)
  • Test: write pattern via PCSC, MCU reads and programs LP5562

Phase 4 — Power Management

  • Characterize energy harvesting power budget with oscilloscope
  • Determine optimal EH voltage/current settings (target: 3.0V, 9.0mA+)
  • Implement SAMD21E STANDBY sleep mode
  • Configure EIC wake on NTAG5Link FD pin
  • Configure EIC wake on hall sensor GPIO
  • Test full boot → program → sleep → wake cycle
  • Measure total system current draw in each state

Phase 5 — NFC Communication Protocol

  • Design SRAM mailbox protocol (command/response frames)
  • Implement MCU-side protocol handler
  • Implement chunked transfer for patterns > 252 bytes
  • Extend ntag5sensor Python tooling with xblink protocol commands
  • Test pattern upload via PCSC reader
  • Test with VivoKey RawNFC app

Phase 6 — Recovery and Safe Mode

  • Implement hall sensor GPIO input with debounce
  • Implement recovery mode detection at boot
  • Recovery behavior: hardcoded default pattern, skip EEPROM, stay awake
  • Set recovery flag in SRAM for phone app detection
  • Test recovery mode end-to-end

Phase 7 — Firmware Update Strategy

  • Evaluate NFC pass-through bootloader feasibility (see DEVELOPMENT_PLAN.md)
  • Evaluate UF2 + NFC hybrid approach
  • Implement chosen update mechanism
  • Test firmware update end-to-end
  • Document update procedure

Phase 8 — Custom PCB (SAMD21E)

  • Port from xiao_m0 BSP to bare atsamd-hal with samd21e feature
  • Remap pin assignments for SAMD21E18A (32-pin QFN)
  • Provide custom memory.x linker script
  • Design PCB schematic (SAMD21E + NTAG5Link + LP5562 + hall sensor + antenna)
  • PCB layout for implant form factor
  • Fabricate and test prototype PCB

Phase 9 — Companion App

  • React Native project setup
  • NFC communication layer (ISO15693 via platform APIs)
  • Pattern editor UI
  • Pattern upload via NFC
  • Firmware version check / status display

Open Questions

Question Status Notes
Energy harvesting power budget TBD Need oscilloscope measurements with LP5562EVM + NTAG5 Click
Optimal LED current per channel TBD Must fit within EH budget, probably 2-5mA/ch
Firmware update strategy Under evaluation NFC pass-through vs UF2 hybrid, see DEVELOPMENT_PLAN.md
NTAG5Link I2C slave address Assumed 0x54 Verify with Click board when jumper available
SAMD21E18A package sourcing Not started Verify QFN-32 availability for custom PCB phase
Antenna design Not started Loop antenna for 13.56MHz, PCB-integrated or wire coil

Hardware Inventory

Item Status Notes
Seeed XIAO M0 Available Dev board MCU (SAMD21G18A)
LP5562EVM Available TI eval module, RGBW LEDs, I2C addr 0x30
NTAG5 Link Click Available, partially wired Missing I2C jumper to XIAO
Hall effect sensor Not available Need to source
ACR1552 PCSC reader Available For ntag5sensor Python tooling