bae64c1e3a
Set up Rust embedded project targeting SAMD21 (thumbv6m-none-eabi) with XIAO M0 BSP for dev board prototyping. Includes LP5562 EN pin control on D0/A0, project documentation (README, CLAUDE.md), phased status tracker, and detailed development plan covering LP5562 driver integration, NTAG5Link I2C driver, pattern storage format, power management, NFC communication protocol, recovery mode, and firmware update strategy. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
127 lines
5.0 KiB
Markdown
127 lines
5.0 KiB
Markdown
# xblink Project Status
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**Current Phase**: Phase 0 — Project Setup
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**Last Updated**: 2026-03-03
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---
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## Phase 0 — Project Setup
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- [x] Initialize git repository
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- [x] Initialize Rust project with `cargo init`
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- [x] Configure `.cargo/config.toml` for thumbv6m-none-eabi
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- [x] Set up `Cargo.toml` with XIAO M0 BSP and embedded-hal 1.0
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- [x] Create `.gitignore`
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- [x] Create initial `src/main.rs` (blink + LP5562 EN pin on D0/A0)
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- [x] Create project directory structure (`src/led/`, `src/ntag5/`, `src/pattern/`, `docs/`)
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- [x] Create README.md
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- [x] Create CLAUDE.md
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- [x] Create docs/STATUS.md (this file)
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- [x] Create docs/DEVELOPMENT_PLAN.md
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- [x] Verify `cargo build --release` compiles
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- [x] Initial git commit
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## Phase 1 — LP5562 Driver Integration
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- [ ] Copy LP5562 driver from `../ntag5-samd21-lp562/src/lp5562.rs`
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- [ ] Define `LedController` trait in `src/led/mod.rs`
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- [ ] Wrap LP5562 driver to implement `LedController`
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- [ ] Add GPIO EN pin control to LP5562 wrapper (D0/A0 hardware enable)
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- [ ] Test LP5562 direct PWM on XIAO M0 + LP5562EVM
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- [ ] Test LP5562 engine programs (breathing, color cycling)
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- [ ] Implement `SimplePwm` driver as second `LedController` implementation
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## Phase 2 — NTAG5Link Driver (MCU-side I2C Slave)
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- [ ] Implement NTAG5Link register map (`src/ntag5/registers.rs`)
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- [ ] Implement EEPROM block read/write via I2C (`src/ntag5/eeprom.rs`)
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- [ ] Implement SRAM mailbox read/write (`src/ntag5/sram.rs`)
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- [ ] Implement session register access
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- [ ] Test EEPROM read/write with XIAO M0 + NTAG5Link Click board
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- [ ] Test SRAM mailbox read/write
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- [ ] Verify round-trip: write pattern via PCSC reader, read back on MCU
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## Phase 3 — Pattern Storage Format
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- [ ] Design binary pattern format (header + engine programs + LED mapping)
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- [ ] Document format in `docs/PATTERN_FORMAT.md`
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- [ ] Implement pattern deserializer (`src/pattern/mod.rs`)
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- [ ] Implement LP5562 engine program builder from pattern data (`src/pattern/engine.rs`)
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- [ ] Implement pattern serializer (for MCU-side EEPROM writes)
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- [ ] Test: write pattern via PCSC, MCU reads and programs LP5562
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## Phase 4 — Power Management
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- [ ] Characterize energy harvesting power budget with oscilloscope
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- [ ] Determine optimal EH voltage/current settings (target: 3.0V, 9.0mA+)
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- [ ] Implement SAMD21E STANDBY sleep mode
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- [ ] Configure EIC wake on NTAG5Link FD pin
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- [ ] Configure EIC wake on hall sensor GPIO
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- [ ] Test full boot → program → sleep → wake cycle
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- [ ] Measure total system current draw in each state
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## Phase 5 — NFC Communication Protocol
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- [ ] Design SRAM mailbox protocol (command/response frames)
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- [ ] Implement MCU-side protocol handler
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- [ ] Implement chunked transfer for patterns > 252 bytes
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- [ ] Extend ntag5sensor Python tooling with xblink protocol commands
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- [ ] Test pattern upload via PCSC reader
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- [ ] Test with VivoKey RawNFC app
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## Phase 6 — Recovery and Safe Mode
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- [ ] Implement hall sensor GPIO input with debounce
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- [ ] Implement recovery mode detection at boot
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- [ ] Recovery behavior: hardcoded default pattern, skip EEPROM, stay awake
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- [ ] Set recovery flag in SRAM for phone app detection
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- [ ] Test recovery mode end-to-end
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## Phase 7 — Firmware Update Strategy
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- [ ] Evaluate NFC pass-through bootloader feasibility (see DEVELOPMENT_PLAN.md)
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- [ ] Evaluate UF2 + NFC hybrid approach
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- [ ] Implement chosen update mechanism
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- [ ] Test firmware update end-to-end
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- [ ] Document update procedure
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## Phase 8 — Custom PCB (SAMD21E)
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- [ ] Port from `xiao_m0` BSP to bare `atsamd-hal` with `samd21e` feature
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- [ ] Remap pin assignments for SAMD21E18A (32-pin QFN)
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- [ ] Provide custom `memory.x` linker script
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- [ ] Design PCB schematic (SAMD21E + NTAG5Link + LP5562 + hall sensor + antenna)
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- [ ] PCB layout for implant form factor
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- [ ] Fabricate and test prototype PCB
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## Phase 9 — Companion App
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- [ ] React Native project setup
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- [ ] NFC communication layer (ISO15693 via platform APIs)
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- [ ] Pattern editor UI
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- [ ] Pattern upload via NFC
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- [ ] Firmware version check / status display
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---
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## Open Questions
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| Question | Status | Notes |
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|----------|--------|-------|
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| Energy harvesting power budget | TBD | Need oscilloscope measurements with LP5562EVM + NTAG5 Click |
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| Optimal LED current per channel | TBD | Must fit within EH budget, probably 2-5mA/ch |
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| Firmware update strategy | Under evaluation | NFC pass-through vs UF2 hybrid, see DEVELOPMENT_PLAN.md |
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| NTAG5Link I2C slave address | Assumed 0x54 | Verify with Click board when jumper available |
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| SAMD21E18A package sourcing | Not started | Verify QFN-32 availability for custom PCB phase |
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| Antenna design | Not started | Loop antenna for 13.56MHz, PCB-integrated or wire coil |
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## Hardware Inventory
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| Item | Status | Notes |
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|------|--------|-------|
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| Seeed XIAO M0 | Available | Dev board MCU (SAMD21G18A) |
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| LP5562EVM | Available | TI eval module, RGBW LEDs, I2C addr 0x30 |
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| NTAG5 Link Click | Available, partially wired | Missing I2C jumper to XIAO |
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| Hall effect sensor | Not available | Need to source |
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| ACR1552 PCSC reader | Available | For ntag5sensor Python tooling |
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