ISO15693 already provides CRC-16 at the transport layer, making
the application-layer CRC redundant. Simplifies header from 6 to
4 bytes, removes crc16_continue/verify_crc, and drops STATUS_BAD_CRC.
Also updates design doc and fixes markdown table formatting.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Pattern entry bytes 108-109 now hold next_pattern (0xFF=loop forever,
0-8=chain to index) and loop_count. MCU will poll LP5562 STATUS register
to detect engine completion and load the successor pattern.
Updated XBLK format spec, Rust Pattern struct (serializer + deserializer),
and React Native app design doc (binary format, data model, resolved
open questions).
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
XBLK binary format for pattern library in NTAG5 upper 1K EEPROM:
- 16-byte header (magic, version, pattern count, active index, CRC-16)
- Up to 9 × 112-byte fixed-size pattern entries
- Deserializer + serializer in src/pattern/mod.rs
- MCU self-provisions hardcoded patterns on first boot (no XBLK found)
- Subsequent boots load active pattern directly from EEPROM
- Python serializer tool for future PCSC-based pattern uploads
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
M3: 5 autonomous LP5562 engine patterns (breathe, heartbeat, slow_pulse,
rgb_cycle, color_wash) with dual LED mode support (RGBW/Mono3) and
2mA/ch current for EH-realistic power budget.
M4: NTAG5Link I2C slave driver with session register reads, EEPROM
write-verify, and NDEF Type 5 text record output. Config check validates
CONFIG_0, CONFIG_1, EH_CONFIG against expected values and writes result
as NFC-readable text. Verified on hardware: config check passes, NDEF
readable via ISO15693 from phone.
Key findings from hardware testing:
- SRAM passthrough arbiter blocks NFC reads while I2C bus is active
(resolves naturally when MCU enters STANDBY — noted in M7 plan)
- NTAG5 must be in I2C slave mode (not master) for MCU communication
- EH config mask set to 0x00 (skip check during external power testing)
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add src/pattern/ module with 3 engine patterns:
- Breathe: smooth ramp up/down (~2.5s cycle, 1 engine)
- Heartbeat: double-pulse with long rest (~1.6s cycle, 1 engine)
- RGB cycle: phase-offset breathing via trigger sync (3 engines)
Patterns support both RGBW and 3-channel monochrome LED modes via
LED_MAP configuration. Main loop cycles through all 3 patterns (8s
each) while LP5562 runs them autonomously — MCU just idles.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add error-resilient firmware with diagnostic LED blink patterns
(3 slow = alive, solid = I2C OK, fast burst = I2C error). Document
EVM external MCU wiring: disconnect P6 EN jumper, power VDD from
XIAO 5V, leave SCL/SDA jumpers in place with MSP430 unpowered.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Reverse-engineered the MSP430 serial protocol on the LP5562EVM:
- I<addr><reg> reads, O<addr><reg><data> writes, status 00=OK / 02=NAK
- EN pin must be jumpered to VDD (MSP430 doesn't drive it after reset)
- CONFIG (0x0B) is write-only, W_CURRENT (0x09) not writable via bridge
- LED cycling verified: all 4 channels respond to direct PWM control
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
The uFR Zero presents as CCID (not serial), so the uFCoder library
cannot communicate with it. Rewrote ntag5_config_check.py to use
pyscard with auto-detection: ACR1552 for full NXP config verification,
generic PCSC for basic tag info. Removed uFCoder library (unusable).
Backed up CCID Info.plist before adding uFR Zero VID:PID entry.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Hall sensor + LP5562 EN wired-AND circuit design (DRV5032FB/FE,
1M pull-up, open-drain topology) with three interaction modes:
boot-time recovery, tap-to-swap, hold-to-confirm recovery
- NTAG5 config check tool (tools/ntag5_config_check.py) using
uFCoder library for ISO15693 transparent mode via uFR Zero reader.
Supports inventory + addressed mode for multi-tag fields.
- Updated DEVELOPMENT_PLAN with I2C bus management notes for
LP5562 (0x30) + NTAG5Link (0x54) shared bus
- Updated README with wired-AND hardware diagram, hall sensor
interaction section, and updated wiring table
- Updated CLAUDE.md with LP5562 EN wired-AND topology docs
- Updated STATUS.md with hall sensor decisions and hardware inventory
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Integrate LP5562 driver from sibling project (ntag5-samd21-lp562)
with full doc comments restored
- Update main.rs with complete M1 test: I2C init, GPIO EN, RGBW cycle
- Rewrite DEVELOPMENT_PLAN.md from waterfall to milestone-based groups
organized by hardware availability (Groups A-E)
- Rewrite STATUS.md with milestone checklist tracking
- Add LP5562 timing constraints and flash script docs to CLAUDE.md
- Add flash_when_ready.sh for auto-flash dev workflow
- Add brainstorm design doc for plan redesign rationale
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Set up Rust embedded project targeting SAMD21 (thumbv6m-none-eabi) with
XIAO M0 BSP for dev board prototyping. Includes LP5562 EN pin control
on D0/A0, project documentation (README, CLAUDE.md), phased status
tracker, and detailed development plan covering LP5562 driver integration,
NTAG5Link I2C driver, pattern storage format, power management, NFC
communication protocol, recovery mode, and firmware update strategy.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
